דרושים » הנדסה » ASIC Verification engineer

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
1 year of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with design sign off and quality tools (Lint , CDC , etc.).

Preferred qualifications:
Master's or PhD in Computer Science or related technical fields.
Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors family.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Knowledge of SOC architecture.
Excellent problem-solving and debugging skills.

Requirements:
Bachelor's degree or equivalent practical experience.
8 years of experience architecting networking ASICs from specification to production.
Experience working with design networking like: RDMA and or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience developing RTL for ASIC subsystems.
Experience in cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:
Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic Random-Access Memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience working with software teams optimizing the hardware/software interface.
Experience architecting networking switches, end points, and hardware offloads.
Experience in a procedural programming language (e.g. C++, Python, Go.).
Experience in estimating performance by analysis, modeling, and network simulation. Ability to define and drive performance test plans.
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience architecting networking ASICs from specification to production.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:
Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
Experience architecting networking switches, end points, and hardware offloads.
Experience working with design networking like: RDMA or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience with Mastery of TCP, IP, Ethernet, PCIE, and DRAM, and familiarity with Network on Chip (NoC) principles and protocols (e.g., AXI, ACE, and CHI).
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
Ability to adeptly estimate performance through analysis, modeling, and network simulation, and drive performance test plans.

Requirements:
Bachelor's degree in Computer Science, a related field, or equivalent practical experience.
10 years of experience architecting networking ASICs from specification to production.
Experience working with design networking like: RDMA and or packet processing and system design principles for low latency, throughput, security, and reliability.
Experience developing RTL for ASIC subsystems.
Experience in cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:
Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience in estimating performance by analysis, modeling, and network simulation, and defining and driving performance test plans.
Experience working with Software teams optimizing the hardware/software interface.
Experience architecting networking switches, end points, and hardware offloads.
Experience in a procedural programming language (e.g., C++, Python, Go).
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.

Requirements:
Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
3 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
Experience with ASIC DFT synthesis, simulation, and verification flow.
Experience in DFT specification, definition, architecture, and insertion.

Preferred qualifications:
Master's degree in Electrical Engineering.
Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).
Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
Experience in SoC cycles, silicon bringup, and silicon debug activities.
Experience in fault modeling.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in Design For Test from DFT architecture to post silicon production support.
4 years of experience with people management.
Experience with multiple projects DFT design and verification, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and common industry tools, DFT and Physical Design flows, and DFT verification flow.
Experience in leading DFT activities throughout the whole ASIC development flow.

Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience in post-silicon Debug, test or product engineering.
Experience in JTAG and iJTAG protocols and architectures.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.

Requirements:
B.Sc. in Electrical Engineering or related field
0-4 years of experience in VLSI verification
Experience with SystemVerilog or Specman (UVM is a plus)
Preferred Qualifications
Experience in any of the following is a plus
Formal or Functional Verification tools
FPGA design verification
Mixed-signal verification
Scripting & automation for verification flows.

Requirements:
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Requirements:
Minimum Requirements:
A VLSI Design Engineer with extensive experience in backend design.
B.Sc./M.Sc. in Electrical Engineering.
Strong understanding of Place & Route flow.

Preferred/Advantageous Qualifications:
Deep understanding of all aspects of Physical construction and Integration.
Experience in Leading Physical Design Projects.
Leadership and mentoring skills.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate, self-learning skills, and ability to work autonomously.

Requirements:
BSc in Electrical engineering/Computer Engineering.
Over 5 years of experience in Logic design.
Experienced in all ASIC flow from definition to implementation.
Experience in design for power- Advantage.
Experience in High-speed I/Fs or algorithm blocks - Advantage.
Knowledge in CDC and low power flow - Advantage.