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לפני 10 שעות
Location: Caesarea
Job Type: Full Time
We are excited to announce that the Silicon One team is undergoing rapid growth, and we have opened multiple positions for Junior C++ Software Engineers!

You'll be joining Silicon One Israeli team which is the core center of our SW and ASIC design. You'll be part of the group driving our groundbreaking next-generation network devices - Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs.

You'll develop Core Software technologies at the heart of tomorrow's leading infrastructure solutions, tackling the entire range of challenges from user-facing API-s, through high-level algorithms, all the way down to firmware.

In this role, you will:

Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed.

Location: Caesarea, Israel.
Requirements:
Minimum Qualifications:
B.Sc or M.Sc Computer Science, Computer Engineering or Electrical Engineering graduate from leading Israeli Universities.
Strong understanding of at least one coding language
Minimum GPA of 88. (Please attach your grade sheet when applying to expedite the recruitment process).

Preferred Qualifications:
You are an ambitious and motivated individual, who enjoys big challenges and can quickly ramp on multiple domains.
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time
We are undergoing rapid growth, and we are looking for a senior P4 Data Plane Developer that will develop the Silicon One network applications.

Meet the Team
Join the Silicon One team developing a unified silicon architecture for web-scale and service provider networks. Our silicon team provides an outstanding, unique experience for ASIC and Software engineers by combining the resources offered by a sizable multi-geography silicon organization with the startup culture and breadth of growth opportunities that working in a smaller team can provide.

Your Impact:
Design and develop data plan software driving the world's most sophisticated infrastructures, using a modern P4 which is a domain-specific language for network devices, specifying how data plane devices (switches, routers, filters, etc .) process packets.
Gain intimate knowledge of world-class silicon and programming models.
Work with architecture and design teams to define the next generation of ASIC products being developed.
Requirements:
Minimum Qualifications:
B.Sc or higher degree in Computer Engineering, Electrical Engineering, or a related field.
3+ years of experience in Software Development or Embedded Development.
Background in Networking (L2/L3 networking technologies).

Preferred Qualifications:
Experience with P4 programming language.
Experience with Python programming language.
A deep understanding of network protocols.
Experience with writing and testing software for high performing and scalable networking products.
GIT, Jira, Jenkins, and CI/CD pipeline tools.
Expertise in diagnosing and resolving intricate network issues using tools and techniques such as packet capture analysis, log analysis, and protocol debugging.
Ability to quickly ramp on multiple, interdisciplinary domains.
Love for solving complex problems.
This position is open to all candidates.
 
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לפני 9 שעות
Location: Caesarea
Job Type: Full Time
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.

As part of our team, youll contribute to the development of our next-generation network devicesSilicon One. Our team operates in a startup-like environment within a stable and leading corporation.
Requirements:
MINIMUM REQUIREMENTS:
A VLSI Design Engineer with extensive experience in backend design.
B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevent background.
Strong understanding of Place & Route flow.

PREFERRED QUALIFICATIONS:
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Experiance in PD CAD with familiarity with Physical Design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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לפני 10 שעות
חברה חסויה
Location: Caesarea
Job Type: Full Time
Your Impact:
Craft and develop software driving the world's most complex infrastructures.
Gain intimate knowledge of world-class silicon and programming models.
Work with architecture and design teams to define the next generation of ASIC products being developed.
Requirements:
Minimum Qualifications:
B.Sc or higher degree in Computer Science or a related field.
Working or academic Software Development experience.
Experience in Low-Level SW Development: C++/ C / Embedded / Etc.
Fluent English.

Preferred Qualifications:
Experience in Python.
Ability to quickly ramp up on multiple, interdisciplinary domains.
Love for solving complex problems.
Experience with networking technologies.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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16/06/2025
חברה חסויה
Location: Caesarea
Job Type: Full Time
We are looking for an experienced Team Lead to contribute to the development of our Artificial Intelligence SDK. This is an exciting opportunity to work with highly talented engineers and be a part of product innovation on cutting-edge technologies in the Artificial Intelligence/Deep Learning domain. If you are an excellent, bright, hands-on engineer with a passion for making a difference apply to join our group!

As a leading software engineer in our group, you will analyze modern Artificial Intelligence workloads, and define and develop our SDK Our set of development tools built and optimized to automatically compile and map AI code to run on our platform. Those tools include optimization algorithms, compilers, simulators, profilers, and more.

You will get a deep understanding of AI-centric SW and HW architectures as well as end-to-end use cases and Deep Learning algorithms/pipelines, work, and interact with external vendors and customers for requirement gathering and correct integration of new features.
Requirements:
Requirements:
BSc/MSc in Computer Science or Computer Engineering from the accredited university.
Proven experience in C++ and Python programing with proven record in large scale SW design.
Managed at least 2-3 software engineers.

Advantage:
Experience with developing compilers, specifically MLIR/LLVM development.
Experience with DL frameworks such as PyTorch or TensorFlow is an advantage.
Experience with deployment of DL Models to Production
This position is open to all candidates.
 
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לפני 9 שעות
חברה חסויה
Location: Caesarea
Job Type: Full Time
Join the Silicon One PHY System Team, a key part of silicon development. You'll be at the forefront of defining, implementing, and validating advanced PHY and system solutions for next-generation network devices.

Your responsibilities will include:
Defining features for future devices utilizing cutting-edge silicon technologies.
Developing and optimizing PHY firmware and calibration processes.
Driving system-level definitions, operations, and post-silicon validation.
Collaborating with cross-functional teams to ensure high-quality deliverables.
Requirements:
Minimum Requirements:
B.Sc/M.Sc in Electrical Engineering or Computer Science.
Hands-on lab work and a strong multi-disciplinary system orientation.
Proficiency in Logic Design and coding.
Understanding of networking principles and protocols.

Preferred Qualifications:
Specialization in Communication and Signal Processing.
Familiarity with C++, Python, and MATLAB.
Strong problem-solving skills and attention to detail.
Effective communicator and quick to learn new concepts.
Ability to create thorough technical documentation.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an IoT sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnect from the IoT. This revolutionary mixture of cloud and semiconductor technology is being used by some of the worlds largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products.
Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm and PepsiCo.

looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.

Responsibilities
Lead the full verification lifecycle and methodologies. Plan, Design and Execute verification of SV/UVM Block level and Full chip environments , creating and execution test plans, tracking progress, and ensuring verification closure across diverse Mix-signals SoC simulation using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
5+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.
Advantages
2+ years of managerial experience. (Only for DV lead)
Knowledge in Low Power technics and UPF standard.
Knowledge with Mix signals SoCs.
Knowledge with SW/HW Co-development
This position is open to all candidates.
 
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לפני 10 שעות
חברה חסויה
Location: Caesarea
Job Type: Full Time
What You'll Do:
You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
Requirements:
Minimum Requirements:
A VLSI Design Engineer with extensive experience in backend design.
B.Sc./M.Sc. in Electrical Engineering.
Strong understanding of Place & Route flow.

Preferred/Advantageous Qualifications:
Deep understanding of all aspects of Physical construction and Integration.
Experience in Leading Physical Design Projects.
Leadership and mentoring skills.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
You will join our Cisco Silicon One team, the epicenter of Ciscos ASIC design. Our engineers handle every aspect of chip design, from definition and architecture to coding, physical design, and signoff.
Your responsibilities will include:
Spearhead innovative switch system design, guiding the process from concept through to mass production.
Collaborate with multi-functional teams in areas such as board design, mechanics, thermal, PCB layout, production, software/firmware, RTL, and more.
Act as the technical focal point and decision-maker for the project.
Conduct hands-on testing in a lab environment and support production and qualification stages.
Define product specifications, develop electrical schematics, and guide component selection and layout processes.
Requirements:
Minimum Requirements:
B.Sc in Electrical Engineering from a leading academic institution.
Over 4 years of experience as a board design engineer, with a strong background in implementing complex hardware projects.
Experience in designing high-speed designs.
Expertise in multi-layer PCB design.
Hardware-oriented, with experience in lab work (measurements/characterization, lab equipment).
Hands-on experience in PCB bring-up and debugging.

Preferred Qualifications:
Demonstrated success in leading multi-disciplinary projects.
Strong project management abilities, determined, with excellent interpersonal skills.
System orientation with multi-disciplinary approach and multitasking capabilities.
This position is open to all candidates.
 
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לפני 10 שעות
Location: Caesarea
Job Type: Full Time
As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.
Requirements:
Minimum Qualifications:
B.Sc./M.Sc. in Electrical Engineering or a related field.
Hands-on experience with one or more DFT features, such as scan insertion, BIST, or boundary scan.
Proficiency in full product lifecycle development, from pre-silicon design to silicon bring-up and production qualification.

Preferred Qualifications:
Experience with Automatic Test Pattern Generation (ATPG) methodologies.
Strong ability to establish and refine DFT methodologies from design phase to high-volume production.
Ability to quickly learn new concepts and adapt to evolving technologies.
Excellent communication and presentation skills.
Strong attention to detail and system-level understanding of networking and silicon solutions.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
founded by the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an IoT sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging things previously disconnected from the IoT. This revolutionary mixture of cloud and semiconductor technology is being used by some of the worlds largest consumer, retail, food, and pharmaceutical companies to change the way we make, distribute, sell, use, and recycle products.

Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm, and PepsiCo.

Were seeking a highly skilled and motivated Senior Research Engineer with deep expertise in digital communication systems to join our world-class team. If you have a strong academic background, at least 5 years of relevant industry experience, and a passion for shaping the future of IoT communication technologies and standards, we want to hear from you!

Responsibilities
Drive the research and development of advanced communication technologies for ultra-low power IoT devices.
Design and evaluate algorithms for digital and wireless communication, including modulation, coding, and channel estimation.
Draft and present technical contributions in standardization bodies like IEEE, 3GPP and Bluetooth - that help shape the future of global communication standards.
Collaborate closely with cross-functional teams including systems, hardware, software, analog, and product.
Analyze technical challenges and provide innovative solutions in constrained RF and communication environments.
Stay up to date with emerging technologies and propose new research directions.
Requirements:
Masters or Ph.D. in Electrical Engineering, Digital Communication, Telecommunications, or a related field.
Minimum 5 years of relevant experience.
Strong theoretical and practical knowledge of digital communication systems.
Excellent analytical, problem-solving, and critical thinking abilities.
Strong verbal and written communication skills, including technical presentation.
Advantages
Hands-on experience with:
Wireless standards (Bluetooth, 5G/3GPP, IEEE 802.15/11)
Simulation tools such as MATLAB or Python
Communication system design and optimization
Prior experience contributing to international standardization forums.
This position is open to all candidates.
 
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