דרושים » תוכנה » Chip Design Engineer

We are looking for talented engineers to help us develop the semiconductor platform which is based on revolutionary architecture.
Take part in the development of cutting edge products within disruptive system architecture. Youll have the opportunity to work on the technologies that power the worlds largest Cloud provider, within a dynamic, open, and fast-paced environment.

We are looking for a Senior DFT engineer to join the DFT design team and help develop the next generation of chips based on a revolutionary architecture. DFT (Design-for-Testability) is a multifaceted job that involves architecture definition, logic design, verification, test patterns generation, chip bring-up and more. As a Senior DFT engineer, you will impact and see the device through its entire lifecycle, from definition stage to mass production. You will work in close collaboration with multiple VLSI engineering groups including chip design, verification, backend, test, reliability and more.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical problems with micro-architecture and solutions, and evaluate design options with performance, power, and area.The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the System on a Chip (SoC)/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and Application-specific integrated circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC level verification.
Communicate and work with multi-disciplined and multi-site teams.

About the job
our company's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets our company's standards of quality and reliability.
As a Chip Infrastructure Engineer, you will plan and execute work in an innovative and fast-paced environment, with a focus on infrastructure that enables design and verification teams to produce the chips that power our company's computing needs. You'll be part of the chip infrastructure team responsible for compute, storage, common chip design components, and front-end tool flows.
In this role, you will work with architects, logic designers, and verification engineers to develop flows to build and verify SoC chip designs. Youll also work closely with software, physical design, silicon bring-up and validation teams to enable a successful software integration, implementation, silicon bringup and deliver quality silicon.
The ML, Systems, & Cloud AI (MSCA) organization at our company's designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company's services (Search, YouTube, etc.) and our companys Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company's services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company's Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Work with partner teams to provide the compute, storage and methodology needs of the chip design, verification and physical design teams.
Collaborate with Application-Specific Integrated Circuit (ASIC) teams to implement tools and methodologies.
Design and implement CAD tools, solutions and methodologies for ASIC development.
Extend the capabilities of third-party tools through their dedicated APIs.
Provide documentation, training, and support to increase end user productivity.

We are seeking best-in-class ASIC Verification Engineers to help deliver the worlds leading CPU's and SoC's. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

NVIDIA is building a new group in Israel, this group delivers security engines and risc-V processor IPs to all of NVIDIA product lines working with all NVIDIA groups around the world. We are looking for inquisitive, motivated engineers with experience to continue to build this new group. As a senior member of our team, you will be responsible for the verification of high-performance, low-power security engines and risc-V processor modules. You will work closely with architects, design engineers, FC verification engineers, and SW teams.

What you will be doing:
Participate in micro-architecture development and document specifications.
Build System Verilog UVM verification environments for IPs in areas of crypto and Risc-V platforms.
Build verification and test plans to get to complete coverage.
Work with the designers in our team to debug and clean all bugs
Deliver the IPs to higher level verification like Cluster, FC and emulation.

About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Frontend Design Engineer, you will take part in central processing unit (CPU) development, a complex and critical blocks of our companys sever System on a Chip (SoC). You will be responsible for microarchitecture and RTL design and implementation of core technology as part of our companys data center SoC products. You'll collaborate closely with architecture, verification, and physical design engineers, creating micro-architectural definitions with RTL coding and running block level simulations.
The ML, Systems & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companys, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define architecture and micro-architecture features, write specifications, and understand implementation tradeoffs (e.g., performance, power, frequency, etc.).
Define the CPU block level design document (e.g., interface protocol, block diagrams, transaction level flow, control registers, pipelines, etc.).
Perform RTL development process (e.g., coding and debug in Verilog, SystemVerilog, or VHDL), function/performance simulation debug, and Lint/CDC/FeV/PowerIntent checks.
Contribute to the SoC level integration, and participate in synthesis, timing/power closure, and silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC-level verification.

We are now looking for a motivated Chip Architecture Engineer to use your creativity to work on the Spectrum Switch with a highly inventive and knowledgeable team.

Our technology has no boundaries! NVIDIA is building the worlds most groundbreaking and state of the art compute platforms for the world to use. Its because of our work that scientists, researchers and engineers can advance their ideas. At its core, our visual computing technology not only enables an outstanding computing experience, it is energy efficient! We pioneered a supercharged form of computing loved by the most fast paced computer users in the world - scientists, designers, artists, and gamers. Its not just technology though! It is our people, some of the brightest in the world, and our company diverse culture make us one of the most fun, innovative and dynamic places to work in the world! At the center of our culture are our core values like innovation, excellence and determination and team, which guide us to be the best we can be.

What you'll be doing:

Be part of the team that defines the Spectrum Switch chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments).

Be part of the team that defines the GPU interconnect protocol, and defines the Architecture for GPU interconnect.

Work with related industry standards & customers on deploying your tech.

Collaborate with teams across teams (physical design, logic design, system software, firmware, applications).

Perform research and analysis for current and future architectures.

Develop Proof of Concepts using our technology, collaborating with our most sophisticated customers on state-of-the-art innovations.

We are now looking for a Senior Chip Design Engineer to join our Switch Silicon team. As a Chip Design Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a design/verification team which develops core units within the Switch silicon.

Micro-architecture of rtl/dynamic verification environments planning for units and modules.

Design RTL/dynamic verification environments of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.

RTL synthesis, timing, supporting verification, and silicon post TO activities.

Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

We are now looking for a Senior Chip Design Engineer to join our Switch Silicon team. As a Chip Design Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What You'll Be Doing:

Work in a design/verification team which develops core units within the Switch silicon.

Micro-architecture of rtl verification environments planning for units and modules.

Design RTL of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.

RTL synthesis, timing, supporting verification, and silicon post TO activities.

Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical issues with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Own Networking Internet Protocols (IP's) Design team including definition, implementation and deployment.
Define IP development methodologies sharing unified blocks within the IP design team.
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.