דרושים » הנדסה » Senior Physical Design Backend Engineer

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6 ימים
Location: Yokne`am and Tel Aviv-Yafo
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Own the special chiplet STA, analyze the timing results, verify correctness and provide budget for the different partitions.

Generate the timing constraints for the STA and the P&R flow.

Be exposed and work on a variety of exciting designs (including high cell count and high frequency), resolving complex timing and congestion problems.

Help to shape clock tree, and effect the work of the different teams (Front end, DFT & BE).

Daily work involves all aspect of STA & chip design: take part in SDC generation & review, actively running & analyzing STA tools, guiding the group during chip closure process, etc'.

Taking part inflows development.

Take part in ramping up new breaking technologies.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.

5+ years of hands-on STA experience.

Experience in Prime Time and signoff methodologies.

Deep understanding of all aspects of Physical construction and Integration.

Great teammate.
This position is open to all candidates.
 
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5 ימים
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.

5+ years of experience in physical design.

Proven experience in RTL2GDS flows and methodologies.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Deep understanding of all aspects of Physical construction and Integration.

Strong background of Physical Design Verification methodology LVS/DRC.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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5 ימים
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

At least 2 years of relevant experience

Proficiency using Python, Perl, Tcl, Make scripting.

Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

Knowledge in process variation effect modelling and experience in design convergence taking into account variations.

Successful track record of delivering designs to production is necessary.

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Ways to stand out from the crowd:

Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus)

Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8196280
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5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you'll be doing:

Join the Tel Aviv group, working on designing the new generation of high-speed ports.

Design for chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area, and performance

Daily work might involve any or all aspects of chip development: Verification, Design, and Micro-Architecture.

Work closely with Firmware and other groups around the globe.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Communication Engineering/Computer Engineering.

5+ years of validated experience in RTL Frontend ASIC Design or Verification (Chip Design).

Strong debugging, problem-solving and analytical skills.

A great teammate with strong communication and interpersonal skills.

Ways to stand out from the crowd:

Knowledge in Specman.

Knowledge in Verilog.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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5 ימים
חברה חסויה
Job Type: Full Time
We are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:
Join accelerators IP group in Beer-Sheva/ Tel-Aviv, working on RiscV platform unit and cache coherence IP.
design for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.
Daily work might involve any or all aspects of chip development: uarch , Design.
Work closely with Firmware and other groups around the globe.
Requirements:
What we need to see:
University B.SC. in Electrical Engineering/Communication Engineering/Computer Engineering.
5+ years of RTL design experience using Verilog/SystemVerilog.
High Level of English.

Ways to stand out from the crowd:
Experienced in CHI protocol or other cache coherence protocols.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
5 ימים
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What youll be doing:

Work in a combined design and verification team that develops front-end design for the Switch silicon, GPU and HCA.

Plan and Design Verification units/blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, and FWinteraction with organization-wide groups.
Requirements:
What we need to see:

Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.

5+ years of experience in RTL verification. Less experienced engineers with high university grades will also be considered.

Experience in full and cluster-level verification is an advantage.

Self-motivated, ability to work independently and drive tasks to completion.

A great teammate with strong communication and interpersonal skills.

Ways to stand out from the crowd:

Knowledge in Specman, Verilog.

Knowledge in Networking.

Great interpersonal skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8196013
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תודה על שיתוף הפעולה
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5 ימים
חברה חסויה
Location: Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Manager to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

We are looking for a highly experienced and motivated Physical Design Manager to lead a team of 1015 engineers as part of our IP development organization. This is a strategic leadership role requiring both deep technical expertise and strong people management skills.

What you will be doing:

Lead and manage a team of 1015 Physical Design engineers, guiding them through all stages of development.

Oversee four concurrent projects, from planning through execution and delivery, working on high-performance and cutting-edge technologies.

Drive technical excellence in floorplanning, synthesis, place & route, timing closure, and physical verification (LVS/DRC).

Collaborate with cross-functional teams, including front-end design, verification, SoC integration, and packaging.

Mentor team members, promote a culture of continuous improvement, and support professional growth.

Ensure timely delivery of project milestones while maintaining high-quality and performance targets.
Requirements:
B.Sc. in Electrical Engineering or a related field; M.Sc. is an advantage.

Minimum of 7 years of hands-on experience in Physical Design.

At least 3 years of proven managerial experience in leading PD teams.

Solid understanding of tools and methodologies in physical implementation (e.g., Synopsys, Cadence, timing analysis, DRC/LVS).

Strong organizational and multitasking skills; ability to manage complex, parallel development streams.

Excellent communication and interpersonal skills.

Fluent in English both written and verbal.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
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5 ימים
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Senior Chip Design Verification Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating new chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you'll be doing:
Take a crucial part in developing NVIDIA's next-generation chip controller.
Design and verification with challenging multi-discipline context.
Take part in the development of all NVIDIA's networking and GPU networking chips and systems.
Requirements:
What we need to see:
B.SC./ M.SC. in Computer Engineering/Electrical Engineering/Communication Engineering.
5+ years of validated experience in ASIC Verification.
High Level of English.

Ways to stand out from the crowd:
Background in Specman.
Knowledge in HDL (Verilog/VHDL).
Knowledge in Mixed Signals, Analog, and Behavioral Models for Verification.
Knowledge in Chip boot and Infrastructures.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for outstanding Chip Design Verification Engineers to join our Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

Come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:
Join Tel Aviv group, working in a combined design and verification team which develops Phy Layer IP within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.
Requirements:
What we need to see:
B.Sc in Electrical Engineering or equivalent experience.
5+ years of validated experience in RTL Frontend ASIC Design or Verification (Chip Design). Less experienced engineers with outstanding academic records will also be considered.
Strong debugging, problem-solving and analytical skills.
A great teammate with strong communication and interpersonal skills.

Ways to stand out from the crowd:
Knowledge in Specman.
Knowledge in Verilog.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8196401
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5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
We are now looking for a Senior Chip Design Integration Engineer to join our Switch Silicon team. As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a design/verification team which develops core units within the Switch silicon.

Micro-architecture of rtl/dynamic verification environments planning for units and modules.

Design RTL/dynamic verification environments of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.

RTL synthesis, timing, supporting verification, and silicon post TO activities.

Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

Work in a FC team, responsible to integrate and verify the Switch at system level.
Requirements:
Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.

5+ years of experience in RTL design/dynamic verification.

Knowledge in network protocols and/or HPC and distributed calculations - advantage.

A team player with good communication and interpersonal skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8196848
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דיווח על תוכן לא הולם או מפלה
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סגור
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
5 ימים
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
We are now looking for a Senior Chip Design Engineer to join our Switch Silicon team. As a Chip Design Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What You'll Be Doing:

Work in a design/verification team which develops core units within the Switch silicon.

Micro-architecture of rtl verification environments planning for units and modules.

Design RTL of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.

RTL synthesis, timing, supporting verification, and silicon post TO activities.

Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.
Requirements:
Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.

5+ years of experience in RTL design.

Knowledge in network protocols and/or HPC and distributed calculations - advantage.

A team player with good communication and interpersonal skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8196567
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