דרושים » הנדסה » Verification engineer

We are looking for a Formal Verification Engineer for our company Networking team!
This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for AI, HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. our company has the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
What you'll be doing:
In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our company's core technology.

We are looking for an excellent Senior Firmware Verification Engineer to join the Firmware team. The company Firmware team develops groundbreaking networking features for AI, cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With many hardworking engineers around the globe, the work environment is complex, results-oriented and fast paced. You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed
What you will be doing:
Work closely with the architecture and different software and hardware design teams.
Implement new features for our company NIC and Switch firmware.
Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.
Collaborate with multi-functional teams including chip design, board designers, Silicon, SW and program managers to debug any FW/validation issues.
Heavily involved with the early modeling and simulation required to produce our outstanding products including schematic and layout reviews on next generation board designs.

We are looking for a Chip-Design Verification Engineer to join our Network Adapter Silicon group. As a Chip-Design Verification Engineer in our Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops core units within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The company System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.
Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.
Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.
Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.
Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).
Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.
Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.
Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.
Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.
Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.

We have been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Our Networking Software Group is rapidly growing, and we are hiring software engineers for the networking Switch Software Verification team. Come and join a diverse group of engineers spread across the globe who come together in small close knit teams to innovative and develop groundbreaking solutions.

As a member of the team, you will be a part of cutting edge Python-based SW project using advanced techniques such as white box testing, multi-thread environment and more. You will gain unique knowledge of how switch operating system works and how large scale networks are constructed. Teams utilize the latest software engineering methodologies and tools in an agile fashion to release on time. Are you ready for this challenge?

What you will be doing:

Design, develop, optimize and maintain APIs, tools and libraries for Verification networking infrastructure

Collaborate with team members, Architects, design, QA teams, and customers (both external and internal)

Design, develop, execute and maintain tests automation for release features.

We are seeking a senior security architect who is passionate about advancing cybersecurity in networking products to join our team. This is an opportunity to work on groundbreaking projects to secure high-performance networking systems.

What you'll be doing:

Collaborate across the company to guide the direction of a converged NIC, working with hardware, software, research, and product teams.

Research, design, develop, and implement architecture solutions (Hardware and software) meeting internal and external security requirements and standards.

Apply innovative hardware security primitives to enable next-generation secure firmware and software supported by innovative hardware.

Collaborate with internal and external partners on the implementation of open-source software.

Architectural modeling, validation, microarchitectural definition, following standards bodies, and developing infrastructure enabling trusted platforms using hardware security methods.

Work with customers, partners to identify and address security issues and threats.

we are a global pioneer of RADAR systems for active military protection, counter-drone applications, critical infrastructure protection, and border surveillance.
Join Our Team as a Radar Performance Analyst!
Are you passionate about radar technology and skilled in performance analysis? Do you thrive in a dynamic, innovative environment where your contributions directly impact cutting-edge solutions? If so, we invite you to explore this exciting opportunity to join our growing team as a Radar Performance Analyst in our Algorithms Department.
Responsibilities:
Collaborate with experienced radar algorithms engineers to optimize radar system performance.
Analyze experiments and field tests to derive technical insights and recommendations for enhancing radar system performance.
Conduct in-depth performance analysis of various radar algorithms to ensure optimal functionality.