דרושים » חשמל ואלקטרוניקה » CPU Logic Design Engineer, Google Cloud, PhD, University Graduate, Start 2025

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with CPU microarchitecture.

Preferred qualifications:
Experience in scripting languages like Python or Perl.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
8 years of experience with microprocessor architecture and related technologies and algorithms.
Experience with CPU architecture performance analysis, tools, and simulators at different abstraction levels (i.e., cycle accurate, functional, emulation).

Preferred qualifications:
Master's degree in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience analyzing workloads and definitions of microarchitectural features.
Knowledge of ARM architecture.
Knowledge of CPU Power Management.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
Experience in full VLSI design cycle.
Experience in RTL implementation of low power designs.
Experience in VLSI development with Verilog, SystemVerilog, System Verilog Assertions (SVA), or VHDL, and with design verification, synthesis, timing/power analysis, and DFT.

Preferred qualifications:
Experience in four or more SoC cycles.
Knowledge of modern high-performance CPU architecture and micro-architecture.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.

Preferred qualifications:
Masters degree in Electrical Engineering or Computer Science.
Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
Experience with CPU implementation, assembly language, or compute SOCs.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
2 years of experience in Automatic Test Pattern Generation (ATPG) methods.
Experience with multiple projects in Design for Testing (DFT) scan design and verification.
Experience with Design for Testing (DFT) techniques and tools, Application-Specific Integrated Circuit (ASIC) Design for Testing synthesis, simulation, and verification flow.

Preferred qualifications:
Master's degree in Electrical Engineering.
Experience working with Automated Test Equipment (ATE) engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).
Experience in System on a chip (SoC) cycles, including silicon bringup and silicon debug activities.
Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
Experience in fault modeling.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.

Preferred qualifications:
Masters degree in Electrical Engineering or Computer Science.
Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
Experience with CPU implementation, assembly language, or compute SOCs.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or SystemVerilog
Experience with reasoning synthesis techniques to optimize RTL code, performance and power with low-power design techniques.
Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).
Experience in reasoning design and debug with Design Verification (DV).

Preferred qualifications:
Experience in coding languages like Python or Perl.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Knowledge of System-on-a-Chip (SoC) architecture.
Knowledge of PCIe, UCIe, DDR, AXI or ARM processors.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
5 years of experience in technical leadership, leading project teams, or setting technical direction.
Experience in managing Design Verification (DV) team.
Experience in verification methodologies, tools, and techniques.
Experience creating chip or subsystem design verification strategies and plans.

Preferred qualifications:
Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
Experience with verification techniques, and full verification life cycle.
Experience in verification of IP/SoC/ASIC.
Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
Experience with ARM instruction set architecture or processor microarchitecture.
Experience in leading teams and delivering projects.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
Experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHDL language.
Scripting experience.

Preferred qualifications:
Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
Experience with chip design flow, physical design, IP integration, and Design for Testing (DFT).
Ability to muti-task, and have a can-do approach.
Excellent communication and facilitation skills.

Requirements:
Bachelor's degree or equivalent practical experience.
8 years of experience architecting networking ASICs from specification to production.
Experience working with design networking like: RDMA and or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience developing Register Transfer Level (RTL) for ASIC subsystems.
Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:
Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience in estimating performance by analysis, modeling, and network simulation. Skilled in defining and driving performance test plans.
Experience working with software teams optimizing the hardware/software interface.
Experience architecting networking switches, end points, and hardware offloads.
Experience in a procedural programming language (e.g. C++, Python, Go.).
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.