You will be responsible for developing and maintaining the physical verification infrastructure required for VLSI design. The primary focus of the role is to develop, implement, and support DRC/LVS rule decks that enable accurate and reliable chip verification according to process and device definitions.
In this role, you will translate device and process requirements into robust DRC/LVS verification code, ensuring consistency between layout, schematic, and manufacturing constraints. The Technician will also support and maintain the verification environment, integrate different EDA tools when required, and develop automation flows to improve efficiency and quality. The position involves close collaboration with internal design teams as well as BU device and process teams in the factory.
Requirements: Technician or Practical Engineer in Software, Computer Science, Electrical Engineering, or Electronics- a must
B.Sc. in the relevant fields- advantage
Relevant experience in physical verification, CAD development, or EDA infrastructure - advantage
Hands-on experience in DRC/LVS code development - advantage
Experience with at least one major physical verification tool (advantage):
o Siemens Calibre
o Cadence PVS
o Synopsys ICV
Familiarity with rule deck languages and scripting (e.g., SVRF, TVF, Tcl, Python, SKILL) - (advantage)
Experience working in Unix / Linux environments.
Understanding layout structures, connectivity extraction, and verification flows.
Experience integrating multiple EDA tools and building automation scripts is an advantage.
This position is open to all candidates.
