Our Unit Level Verification Team is looking for an experienced verification engineer to be involved in the development of our future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like:
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.
Requirements: BSc in electrical engineering, computer engineering, or computer science.
8+ years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++).
System Verilog writing skills, preferably in OVM/UVM.
SW embedded experience, C/C++ skills.
TestPlan defining and Coverage-Driven Verification experience.
3rd-party IPs integration testing experience.
Waveform debugging with the latest EDA tools, root-cause bugs independently.
Nice to have:
Skills in scripting Perl/Python.
Knowledge in Industry Standard protocols such as AXI/OCP/APB.
This position is open to all candidates.