דרושים » הנדסה » Field engineer

job overview:
join our gpu hardware verification team in raanana, israel, and help shape the future of the world's most widely deployed gpu architecture - mali. as a staff hardware Verification engineer, you will play a key technical role in verifying advanced gpu components and subsystems, working alongside architects, designers and Verification engineers to deliver high-quality, industry-leading graphics technology. you'll contribute to complex verification environments, solve challenging technical problems and help drive continuous improvements to our verification methodologies and flows.
responsibilities:
develop and execute verification plans for advanced gpu components and subsystems.
develop and maintain ai tools, agents, and skills to support our engineering teams and workflows.
build, maintain and enhance robust verification environments using systemverilog and uvm.
apply coverage-driven, constrained-random and, where appropriate, formal verification techniques to achieve comprehensive functional coverage.
debug complex functional issues and work closely with design and architecture teams to identify and resolve root causes.
contribute to block-level and system -level verification, including environment integration and regression analysis.
improve verification methodologies, automation, scripting and continuous integration flows to increase quality and efficiency.
participate in verification reviews and support verification sign-off activities.
share technical knowledge and collaborate with colleagues across the wider gpu engineering organisation.

We are seeking a senior ATE Software Engineer to design, build, and deploy our next-generation automated manufacturing test platform for advanced telecom, high-density switching, and optical networking hardware.
In this role, you will bridge the gap between R&D hardware/firmware teams and high-volume manufacturing lines. You will take ownership of ingesting, refactoring, and consolidating disparate R&D scripts, diagnostic tools, and legacy software into a single, scalable, production-grade test platform.
We expect you to leverage modern AI-assisted development tools and workflows to maximize engineering efficiency, accelerate delivery timelines, and build highly robust, self-healing test automation. You will deploy test stations across global Contract Manufacturers (EMS/ODM), actively stabilize production lines through bring-up and ramp-up, and drive continuous test maintenance and root-cause failure analysis (RCA).
Key Responsibilities
Test Platform Architecture & Software Development:
Design, develop, and productize robust, modular test software frameworks for board-level (PCBA) and system-level manufacturing testing across multiple product lines and manufacturing sites.
Codebase Unification & Refactoring:
Consolidate and standardize R&D diagnostic libraries, silicon validation scripts, and firmware tools developed across various environments (Python, C# / Visual Studio, VB, ATEasy, Linux) into a unified, maintainable test execution engine.
AI-Accelerated Development & Workflow Automation:
Actively integrate Generative AI tools and AI coding agents into your daily workflow to accelerate code conversion/refactoring, automate test case synthesis, generate edge-case validation scripts, and enhance overall codebase resilience.
Production Line Deployment & Stabilization:
Deploy test stations and fixtures to local and overseas EMS/CM production lines. Monitor, debug, and fine-tune test execution during NPI and ramp-up phases until yield, takt time, and test stability targets (CPK / First Pass Yield) are achieved.
Failure Investigation & Intelligent RCA:
Investigate complex system-level and component-level test failures. Utilize advanced log analysis, structured telemetry, and pattern recognition to drive root-cause investigations and implement preventive software/hardware fixes.
Ongoing Test Maintenance & Optimization:
Provide continuous operational Production line support and maintenance, bug fixes, software updates, and station cycle-time optimizations for active mass-production lines.
R&D Collaboration & Test Specification:
Collaborate closely with Hardware, Firmware, and Validation teams during early design phases to define test specifications, drive Design for Testability,
Documentation & Technical Reporting:
Author and maintain comprehensive testing documentation, Standard Operating Procedures (SOPs), test coverage matrices, and detailed failure analysis reports.

The System team defines and develops cutting-edge 5G technology. In this role, you will lead the system team responsible for defining our next-generation modem products and developing modem algorithms, working at the intersection of research, system design, and implementation.
Responsibilities
Lead a team of senior system and algorithm engineers responsible for developing innovative 5G modems.
Partner closely with VLSI and SW teams implementing the modem HW and SW and align on system definitions with implementation constraints.
Develop and maintain deep expertise in cellular standards and their implications for modem design.
Lead system and algorithmic research, balancing trade-offs between DSP/SW/HW implementations, performance, implementation cost, real-time constraints, and time-to-market.
Own system definitions, requirements, and implementation from initial research through simulation to official release, including MATLAB/C/C++/SystemC modeling and specification documentation.
Mentor and grow team members, fostering technical excellence and professional development.

We are looking for an NPI & System Product Engineer to drive the transition of advanced networking switches and data center infrastructure systems from late-stage R&D validation & NPI into scalable mass production.
In this role, you will lead the handoff from DVT completion into PVT entry, support the setup and deployment of new production lines at global Contract Manufacturers, and execute capacity ramp-up plans toward High-Volume Manufacturing. You will serve as the technical operational link between R&D design/NPI teams and factory lines, ensuring line balancing, fixture readiness, yield optimization, and hands-on root-cause failure analysis (RCA).
Key Responsibilities
Production Readiness:
Support the technical handoff from R&D DVT exit to Operations PVT readiness.
Track and verify closure of open DVT hardware issues, check BOM readiness, and validate manufacturing gating criteria before mass production.
Execute PVT build plans to ensure product design tolerances align with factory process capabilities.
New Production Line Setup & Deployment:
Participate in the setup, line balancing, and deployment of new manufacturing lines and assembly workcells for chassis and full-rack integrated systems at CM facilities.
Validate physical workstation setups, line assembly flows, operator guidelines, and improve processes.
Verify assembly fixtures, press-fit tooling, and automated test stations during new line deployment.
Create and maintain production test procedures.
Capacity Ramp-Up & Takt Time Optimization:
Monitor station takt times, identify line bottlenecks, and drive cycle-time reduction initiatives.
Support the duplication and operational verification of line fixtures, tooling, and test stations to meet capacity scaling targets.
Track production ramp-up from pilot runs through full-rate High-Volume Manufacturing.
System Product Engineering & Yield Optimization:
Monitor key manufacturing metrics across PCBA & box-build assembly lines: First Pass Yield (FPY), Line Fallout, and Scrap Rate.
Use Statistical Process Control (SPC) and factory telemetry logs to identify systemic yield detractors.
Assist in refining production test limits, calibration procedures, and screening guardbands during volume ramp.
Root Cause Analysis (RCA) & Debugging:
Perform hands-on failure triage on system-level dropouts, intermittent hardware faults, and line fallouts during PVT and ramp-up.
Use schematics, Cadence Allegro board layouts, scopes, JTAG, and diagnostic tools to isolate component vs. process defects.

The AI VLSI department develops top notch NPU that enables the execution of state-of-the-art LLMs, Generative AI models, and neural networks with exceptional performance, impacting multiple hardware and software teams across the company facing amazing PPAA challenges of the edge market.
In this role, as VLSI Team Leader in the AI VLSI department, you will lead a team of engineers developing cutting edge VLSI products such as - DSP, HW accelerators and AI Processors for the edge market, with full responsibility on the Front-End Design.
You will drive the development of robust, scalable, and efficient VLSI design, working closely with global Architecture, hardware simulator and Software teams to shape our companys next generation of AI solutions.
We are looking for an exceptional hands-on leader with strong technical expertise, proven experience leading VLSI Front-End Design engineers, and a track record of delivering complex, state-of-the-art products on time and in production ready quality.
The ideal candidate is execution-driven, innovative, and passionate about building high-performing team and cutting-edge AI technology.
Responsibilities
Manage and lead a team of Front-End Design engineers.
Be accountable for the teams development lifecycle, including architecture, development, validation, and release, focusing on meeting PPAA targets.
Lead development of advanced VLSI IPs for AI processors, DSP and HW accelerators while continuing pushing the VLSI design methodologies, procedures, sign off and AI tools assimilation to its next level.
Support system bring-up, debugging, and customer-facing activities when needed.

we have been elevating computer graphics, pc gaming, and accelerated computing for more than 25 years. today, we're tapping into the unlimited potential of ai to define the next era of computing. as a member of our team, you'll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. come join the team and see how you can make a lasting impact on the most groundbreaking technologies.
our networking bu group is seeking to hire an expert firmware design engineer for the ethernet switch firmware core team. the next generation of switches are a crucial component of the most innovative ai and cloud computing networks in the world. as a member of the ethernet firmware team, you will craft and develop the firmware abstraction layer in the eth switch. this role will require you to participate in the design & development of firmware while working closely with hardware and architecture team to ensure timely delivery of our products to the market.
what you'll be doing:
highly involved in the entire software development process from architecture to integration testing of firmware for the spectrum asic product line.
work with hw & asic team to provide insights into developing the next gen of the groundbreaking of silicon and systems.
design and implement algorithms to improve system scale and performance.
work with higher layer software teams to debug issues reported by customers (internal and external).
design, implement and integrate new features according to the product roadmap.
have a new insight on how to improve our software? why not! bring your ideas to life by innovating during our hackathons
collaborate with other r&d teams around the globe.

As a senior compiler engineer, you will own the design and development of our companys open source based toolchain and graph compiler. You will drive technical solutions end-to-end, deliver compiler capabilities across all our company hardware targets, and help mentor engineers. Our team embraces an AI-agentic development flow, leveraging AI coding agents to accelerate engineering productivity, and we are looking for engineers who champion this approach.
Responsibilities:
Design and develop our companys open source based toolchain targeting custom DSP and NPU architectures.
Drive design and delivery of graph compilation flows: transformations, operator mapping, and code generation.
Champion AI-agentic development practices - integrating AI coding agents into day-to-day engineering workflows.
Own complex components end-to-end, from architecture and design through implementation and delivery.
Provide technical guidance and mentorship to engineers; conduct code reviews.
Collaborate with hardware architecture, algorithms, and software teams globally.
Analyze and optimize toolchain output for performance and correctness across our company processor families.

we are seeking a highly motivated Power Integrity Engineer to join our Hardware Engineering team. In this role, you will be responsible for defining, analyzing, simulating, and validating power delivery networks (PDNs) for next-generation networking platforms supporting high-performance ASICs, advanced SerDes interfaces, optical modules, and AI-scale networking systems.
You will work closely with hardware architects, PCB designers, ASIC teams, signal integrity engineers, mechanical engineers, and manufacturing partners to ensure robust power delivery, optimal system performance, and successful product deployment.
Responsibilities
Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production.
Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices.
Perform pre-layout and post-layout PI simulations using industry-standard tools.
Establish target impedance requirements and validate compliance across all power rails.
Analyze DC voltage drop, AC impedance, transient response, and power distribution performance.
Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing.
Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.
Develop power integrity design guidelines and best practices for next-generation networking products.
Support schematic reviews, layout reviews, and design sign-off activities.
Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.
Investigate and resolve PI-related issues during board bring-up, validation, and production.
Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance.
Drive continuous improvement of PI methodologies, simulation flows, and validation processes.

We are seeking a highly skilled and experienced multidisciplinary engineer with a strong background in system design to join our team. In this role, you will contribute to our upcoming projects and play a key part in the rapid expansion of the Ethernet market.
As a such, you will be responsible for developing high-speed digital and analog circuit boards used in Ethernet products. Your duties will include designing board schematics, overseeing PCB layout, and conducting lab . Additionally, you will be responsible for evaluating new hardware solutions, providing technical leadership in troubleshooting and reviewing schematics, layouts, and design for manufacturability (DFM), as well as managing components selection.