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לפני 1 שעות
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Required Micro-Architect, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Lead Design Activities at IPs, SubSystems(S.S) and SoC.
Define the block-level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up, as well as test plan development and coverage analysis for block and SOC-level verification.
Communicate and collaborate with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
8 years of experience architecting networking ASICs from specification to production or equivalent experience.
4 years of experience in technical leadership.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Experience in micro-architecture, RTL Design, verification, design quality checks, physical design aspects of RTL coding, and power.

Preferred qualifications:
Experience architecting networking switches, end points, and hardware offloads.
Experience working with design networking: RDMA or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience working with software teams optimizing the hardware/software interface.
Proficiency in a procedural programming language (e.g., C++, Python, Go).
Knowledge of TCP, IP, Ethernet, PCIE and DRAM.
Familiarity with Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).
This position is open to all candidates.
 
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לפני 10 דקות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design Engineer, Cloud, Networking
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Lead an ASIC subsystem and understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Implement designs in SystemVerilog.
Collaborate with software, verification, and physical design stakeholders to ensure the designs are complete and correct.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience architecting networking ASICs from specification to production.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience architecting networking switches, end points, and hardware offloads.
Experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience working with software teams optimizing the hardware/software interface.
Experience in TCP, IP, Ethernet, PCIe, DRAM, Network on Chip (NoC) principles and protocols.
Experience in a procedural programming language (e.g., C++, Python, Go).
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
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לפני 1 שעות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SOC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with reasoning synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power and design techniques.
Experience in reasoning design and debug with Design Verification (DV).
Preferred qualifications:
Experience with a scripting language like Python or Perl.
Experience with design sign-off and quality tools (e.g., Lint, clock domain crossing (CDC), etc.).
Knowledge of System on a chip (SOC) architecture and assertion-based formal verification.
Knowledge of design techniques.
Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate SDRAM (DDR), Advanced Extensible Interface (AXI), ARM processors.
This position is open to all candidates.
 
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לפני 8 דקות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure activities.
Contribute to test plan and coverage analysis of the block and SoC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).
Experience with SoC or IP architecture.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Knowledge of high-performance and low-power design techniques, assertion-based formal verification, Field-Programmable Gate Array (FPGA) and emulation platforms, and SoC architecture.
Knowledge in one of the following areas such as Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), High-bandwidth memory (HBM).
Excellent problem-solving and debugging skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8843824
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תודה על שיתוף הפעולה
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לפני 5 שעות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in RTL Design cycle from IP to SoC and from specification to production.
8 years of experience in Technical leadership.
Experience in the following areas: RTL Design, Design Quality checks, Physical Design aspects of RTL coding, and Power.
Preferred qualifications:
Experience with synthesis techniques to improve Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience with Design For Test and its impact on Design and Physical Design.
Experience with a scripting language like Python or Perl.
Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, CHI, Fabrics, and ARM processors.
Knowledge of SOC architecture and assertion-based formal verification.
Knowledge of high performance and low power design techniques.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8843034
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לפני 4 שעות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Networking Silicon Architect, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a part of the team, you will define solutions for high-performance network accelerators and interconnects in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, with close collaborations with data center systems and Software teams. You will participate in the design, architecture, documentation, and implementation of the next generation of data center networking infrastructure.
You will be responsible for performance analysis for an end-to-end networking stack using your deep knowledge of high speed network infrastructure.
We're behind groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Evaluate different silicon solutions for executing our data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and advanced silicon integration technologies.
Design high-performance hardware/software interfaces.
Collaborate closely with system, software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
Drive vendor execution in various engagements: standard component roadmaps, build to specification, and co-developments.
Contribute to the evaluation of future ASIC designs and general architecture.
Requirements:
Minimum qualifications:
Bachelor's degree or equivalent practical experience.
15 years of experience experience architecting networking ASICs from specification to production.
Experience working with network architecture and system design principles for low latency, high throughput, security, and reliability.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Experience in architecting networking and ASIC IPs.
Preferred qualifications:
Mastery of TCP, IP and Ethernet protocols.
Experience working with software teams optimizing the hardware/software interface.
Experience with scripting languages, particularly Python and shell.
Deep understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
Deep understanding of complex, large-scale ASIC and SoC architectures.
Adept in estimating performance by analysis, modeling, and network simulation. Skilled in defining and driving performance test plans.
This position is open to all candidates.
 
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לפני 1 שעות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Requred SoC Power Architect, Cloud, Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Power Architect, you will not just design chips; you will define the energy efficiency of the infrastructure that powers our services worldwide.
In this role, you will be at the intersection of architecture, logic design, physical implementation, and system software. You will own the power architecture for next-generation custom SoCs (System on Chips), making critical trade-offs between performance, thermal constraints, and power delivery to build the most efficient computing platforms on the planet.
Responsibilities
Define and own the SoC power architecture, including complex power domains, clocking structures, and power delivery network (PDN) solutions to achieve optimal performance-per-watt.
Architect sophisticated power management policies, including dynamic voltage and frequency scaling (DVFS), power gating, and state strategies. Define the hardware/software interface for the Power management unit (PMU) and provide power management specifications.
Lead collaboration across architecture, RTL, physical design, packaging and validation teams to establish power budgets and specifications. Ensure power requirements are met from concept to tape-out.
Develop high-fidelity power and performance models to evaluate architectural features early in the design cycle. Drive pre-silicon power estimation and analysis to guide design decisions.
Lead post-silicon power analysis, correlating lab measurements with pre-silicon models to close the loop and improve future methodologies.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
10 years of experience in ASIC/SoC architecture or design with a focus on power optimizations.
Experience developing or using power and performance modeling tools to drive architectural trade-offs.
Experience in low-power design techniques (e.g., UPF/CPF, multi-voltage islands, power gating, clock gating, etc.) and on-chip power management IP.
Preferred qualifications:
Masters degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience in the design and analysis of full-chip power integrity, including interactions between clocking, reset, and power sequencing.
Experience with post-silicon bring-up, power calibration, thermal management, and debugging in a lab environment.
Experience with data center or server SoC power architecture and management requirements.
Experience with industry-standard EDA power tools (e.g., Conformal LP, Power-Artist, PrimeTime-PX, Joules) and simulation environments.
Familiarity with modern workload analysis (AI/ML, transcoding, networking) and their impact on SoC power profiles.
This position is open to all candidates.
 
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לפני 4 שעות
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design Engineer, Edge AI, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
3 years of experience with RTL development for ASIC subsystems using Verilog.
Experience with speed interfaces such as PCIe, InfiniBand, and their low latency, security, and reliability principles.
Experience with micro architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience with scripting languages (e.g., Python or Perl).
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
Knowledge of FPGA, emulation platforms, and SoC architecture.
Knowledge of assertion-based formal verification.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8843190
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לפני 19 דקות
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SOC DFT Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in Automatic Test Pattern Generation (ATPG) methods.
Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
Experience in leading DFT activities throughout an ASIC development flow.
Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience in JTAG and iJTAG protocols and architectures.
Experience in post-silicon test or product engineering.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 4 שעות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Edge-AI SOC Verification Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead the verification of an edge AI IP, to be used in edge-AI products.
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Code development of verification features and capabilities, and participate in RTL debug.
Work closely with architecture, software, design, and physical design stakeholders to make technical decisions and represent project status throughout the development process.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
10 years of experience working with hardware verification languages (e.g., SystemVerilog/Specman), design verification methodologies (e.g., UVM), and chip design flow.
4 years of experience in people management, developing employees.
Experience in leading chip verification teams through the full lifecycle from concept to delivery.
Experience in creating chip or subsystem design verification strategies and plans.
Preferred qualifications:
15 years of experience in verification of complex SoC/ASIC.
8 years of experience managing verification teams.
Experience in chip design/verification of AI/ML logic.
Experience with industry verification techniques, including complementary techniques such as Formal Verification, and Emulation.
Experience in Low Power Verification.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843183
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לפני 26 דקות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design Verification SoC Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive cutting-edge distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Work closely with Architecture, Software, Design, and Physical Design stakeholders to make technical decisions and represent project status throughout the development process.
Develop verification features and capabilities, and participate in RTL debug.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
10 years of experience working with hardware verification languages (e.g., System Verilog/Specman), design verification methodologies (e.g., Universal Verification Methodology (UVM)) and chip design flow.
Experience in leading chip verification teams through the full lifecycle from concept to delivery.
Experience in creating chip or subsystem design verification strategies and plans.
Preferred qualifications:
15 years of experience in verification of complex SoC/ASIC.
10 years of experience managing verification teams.
Experience in chip design/verification of high performance AI/ML accelerators.
Experience with industry verification techniques, including complementary techniques such as formal verification, and emulation.
Experience in low power verification.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843810
סגור
שירות זה פתוח ללקוחות VIP בלבד