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לפני 2 שעות
Location: Haifa and Hod Hasharon
Job Type: Full Time
We are looking for an architect to work on the invention and development of new SW visible CPU technologies to improve performance of SW scenarios related to memory ordering, memory coherency, multithreading, synchronization, memory safety, caching, etc.
The minimal tasks of this role are:
1. Modeling of new memory related architectural features in the existing CPU performance simulator
2. Development of performance tests or adaptation of existing workloads to be suitable for simulation
3. Conducting performance studies for the workloads of choice either in the performance simulator or on a real chip
4. Develop analysis, conclusions and recommendations based on the above activities
The role can comprehend much more than that depending on the skills, talent and experience of the candidate creating a career path over time. For example, to invent new instructions and mechanisms to overcome significant performance bottlenecks in these areas, refinement and further development of ideas provided by others. Possible participation in development in additional domains
If you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!
Requirements:
Four or more years of experience in one or more of the following roles in the memory cluster of an Out of Order CPUs:
Architecture or micro-architecture definition.
Performance modeling and studies.
RTL implementation.
Verification of Multithreading.
Education: Academic degree in Computer Engineering or Computer Science
Advantages:
Knowledge and experience in memory ordering architecture.
HW or SW Experience in inter-thread synchronization.
Knowledge of the arm Instruction Set Architecture.
Skills:
Good verbal English skills.
Good interpersonal skills
Team player.
This position is open to all candidates.
 
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1 ימים
דרושים בהקריה הרפואית רמב"ם
מיקום המשרה: חיפה
סוג משרה: משרה מלאה
* תכנון והובלת פתרונות מקצה לקצה, תוך שילוב בין דרישות עסקיות, תהליכים מקצועיים, מערכות ליבה ופלטפורמות נתונים
* השתלבות בתפקיד רוחבי, בעל השפעה משמעותית על האופן בו פתרונות טכנולוגיים מתוכננים, מחוברים ומיושמים בבית החולים
* עבודה בסביבה ארגונית מורכבת ומרובת ממשקים
דרישות:
* תואר ראשון בתחום רלוונטי
* ניסיון מעשי קודם בארכיטקטורת פתרונות מארגון בינוני-גדול
* ניסיון בתכנון והטמעה של פתרונות מרובי ממשקים
* ניסיון בשילוב פלטפורמות דאטה כחלק מארכיטקטורת פתרון
* יכולת עבודה עם גורמים עסקיים וטכנולוגיים ועם ספקים
* ניסיון בסביבה היברידית ענן On Premise - יתרון
* היכרות קודמת עם עולם הרפואה, בדגש על FHIR ו- OMOP - יתרון משמעותי

כישורים נוספים
* ראייה מערכתית
* יכולת תכנון ברמה גבוהה
* הבנה של תהליכים ארגוניים
* יכולת לחבר בין צורך מקצועי לפתרון טכנולוגי יישים המשרה מיועדת לנשים ולגברים כאחד.
 
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לפני 1 שעות
Location: Hod Hasharon and Haifa
Job Type: Full Time
Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.
Requirements:
BSc or higher degree in Computer Science/Engineering or related discipline from a leading university. (Alternatively, exceptional proven track record in similar tasks)
3+ years of experience in one or more of following disciplines: development of simulators/emulators for CPUs, definition of CPU features, HW/SW co-design, Low level performance profiling and optimization of SW with exposure to CPU ISA
Fluent spoken and written English
Behavioral skills: Team player. Interpersonal skills needed to collaborate with colleagues towards achieving a technical goal
Advantageous qualifications:
Experience in SW/HW codesign or in definition of new instructions will be a great advantage
Familiarity with dense compute workloads and analysis (e.g., AI, HPC, financial, etc.)
Familiarity with Vector Architectures.
This position is open to all candidates.
 
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לפני 1 שעות
חברה חסויה
Location: Hod Hasharon and Haifa
Job Type: Full Time
Required Senior CPU Core Architect
Job Description
The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.
Requirements:
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
At least 20 years of experience in one of the leading CPU companies
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
QUALIFICATIONS
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 1 שעות
Location: Hod Hasharon
Job Type: Full Time
Required Research Intern: Next-generation Computer Architecture for Racks and SuperPods
Responsibilities:
The research focuses on designing next-generation rack and SuperPod architectures that combine elasticity through resource pooling with optimal performance enabled by holistic co-design across applications, parallel programming models, interconnect fabrics, and compute, memory, and switch chip architectures. On the communication side, the work architects scalable, high-bandwidth, and low-latency scale-up fabrics across multiple chips at rack and SuperPod scale. On the memory side, it explores richer protocol semantics beyond traditional load/store operations to reduce unnecessary data movement and rethinks memory hierarchies to expose large-scale capacity with near-local latency. On the compute side, it analyzes the requirements of General Compute and Generative AI workloads and their parallel programming models to fully leverage large-scale system resources.
Investigate and prototype new architectural features, including but not limited to:
o Tiered Memory: Explore advanced memory organizations, including hardware-managed caching, to enable software-transparent, fine-grained promotion and demotion of cache lines across the memory hierarchy.
o Prefetching/Speculation: Evaluate and design existing and next-generation hardware prefetching and speculation mechanisms to effectively hide local and remote memory latencies at rack and SuperPod scale.
o Near-Memory/Network Processing: Develop support for key primitives executed at the memory and network layers to minimize unnecessary data movement across sparse, dense, and pointer-based data structures.
o Workload-Centric Co-Design: Study optimal parallelization strategies at rack and SuperPod scale for both General Compute and Generative AI workloads, and design dedicated hardware support for widely used parallel programming primitives such as RPCs and collective communication.
Write reports and papers on the research results and present them.
Requirements:
MSc in Computer Science, Electrical Engineering, or related field.
Background in Computer Architecture and Computer Fabrics is a must.
Creativity and the ability to think outside the box to develop innovative technologies.
Research experience in at least one of the following areas:
o Computer Architecture: Modern cache hierarchies, cache coherence protocols, memory systems, hardware prefetchers, and the memory-side of the core microarchitecture.
o Scale-up Fabrics: NVLink, UALink, CXL, UPI, IF, or PCIe.
o Parallel programming models: Collective libraires (NCCL or RCCL) and RPCs (gRPC or Thift).
o Workload optimization: General Compute and Generative AI workload composition (internals) and parallelization expertise at the scale of the rack or SuperPoD in both cloud and HPC environments.
Excellent analytical, problem-solving, and system-level thinking skills.
Strong interpersonal skills, with a collaborative spirit and the ability to work independently.
This position is open to all candidates.
 
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לפני 1 שעות
Location: Hod Hasharon and Haifa
Job Type: Full Time
Required Computing Network & System Architecture Group Leader
In this role, you will be responsible for several teams of architects, engineers and software developers, all working together to conduct state-of-the-art R&D in system and network architecture. As the group lead, you will guide and mentor the individual team leads, and also conduct hands-on work leading architecture, technology innovation and technical planning and of high-performance computing cluster network, which oriented at AI, HPC, and big data.
Responsibilities:
You will perform a wide range of duties including:
Architecture Innovation:
Deeply analyzing the advantages and disadvantages of mainstream network systems, to find opportunities for network architecture innovation;
Insight into the technology developing trend of the high-performance computing network field, and leading the corresponding technology planning.
Exploring new architectures of high-performance computing network systems and efficiently integrating communication library, topology, and network protocol to solve performance bottlenecks.
Technical breakthroughs in networking and cluster routing algorithm:
Analyzes computing cluster network performance and leads the development of computing cluster network technologies
Research and optimize the heterogeneous interconnection topology of key computing chips to continuously improve the key competitiveness of Huawei computing heterogeneous chipsets
Responsible for the research of data center network technologies, and guide network topology design and routing algorithm development
Group leadership:
Lead the development of a comprehensive system architecture for AI Fabric and HPC Fabric solutions
Manage and mentor highly skilled team leaders, to ensure that the group operates together in pursuit of common goal
Foster a collaborative and innovative work environment
Provide technical guidance and support to team members
Collaborate closely with cross-functional teams internationally, including hardware, software, and ucode design teams, to ensure alignment of architectural decisions with product and platform common objectives
Initiate and supervise collaborations with top academic researchers in Israel and abroad
Stay up to date with emerging technologies and industry trends in AI, HPC and big data industries
דרישות:
At least 10 years of hands-on experience in system architecture design, or equivalent research experience
Demonstrated experience in leading R&D team
Familiarity with high-performance computing cluster services and system architectures, such as AI, HPC and big data.
In-depth understanding of computer networks, communication libraries, and design of AI or HPC cluster networks
Key qualifications you hold include:
Ability to work in a team environment; actively seek out resolution to issues with the team and work co-operatively to build a coherent system; Team-working and excellent inter-personal communication skills.
High level of self-reliance and an autonomous target-oriented work style, can do attitude, eager to learn new things and ready to think outside the box
Ability to work on a schedule, even for un-schedule-able issues such as inventiveness
Experience with network system of AI, HPC or big data cluster
Demonstrated capability in several items from the list below:
o Deep understanding of computer network protocol and network topology of computing cluster
o Familiarity with communication library, such as OpenMPI/NCCL
o Extensive experience in leading the network architecture design of computing cluster
o Experience with implementing routing algorithm
o Familiarity with network specifications of CPU/Network Processing Unit/ Neural Processing Unit/Switch chip
Fluent in written and spoken English
Advantage:
You hold a Doctors degree or above in the field of computer science, electrical and electronic engineering or in a similar background in Research & Development
Publications in reputed jou המשרה מיועדת לנשים ולגברים כאחד.
 
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חברה חסויה
Location: Haifa
Job Type: Full Time
We are looking for an OS expert with strong knowledge in the Linux Kernel. As a Linux Operating System architect, you will be responsible to work with system and SW architecture teams to define OS solutions to satisfy customer requirements for the autonomous vehicle world. This involves security and connectivity components in our Safety critical Linux OS involving both the Kernel and the user space worlds.
This is an exciting and unique opportunity to work with highly talented Linux OS team and be a leader in the development of the Linux as a platform for the Safety Critical Automotive industry.
What will your job look like:
Defining and designing OS solutions for the security and high-speed connectivity requirements.
Conducting PoC activities to verify architectural decisions and resource allocation involving SW Simulators.
Writing architectural design specification documents, defining KPIs and testing criteria.
Working with the development teams closely to review design and test plan documents.
Performing performance analysis to maximize performance and optimize HW utilization while maintaining the real time behavior.
Requirements:
Strong knowledge in Operating Systems in general and experience with the Linux Kernel specifically.
Proven experience in writing architectural specifications and conducting architectural reviews.
Strong experience in performance analysis and debugging techniques.
Experience with the MIPS & RISCV HW architecture and their implementation in the operating system.
Previous experience in PCIe and Security is a big advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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14/09/2026
חברה חסויה
Location: Hod Hasharon
Job Type: Full Time
we are looking for a Sr. Memory Architect.
A senior memory architect to lead the development of Novel NVM modules in advanced nodes using state-of-the-art EDA tools
Proven ability to lead a memory design from the architecture exploration phase, through block level design & layout up to full module assembly, verification & characterization
Interaction with product marketing & customers to analyze & propose memory architectures meeting the needs of the customer
Requirements:
Knowledgeable in all aspects of memory circuit design, analog design, timing & power optimization, and Design for Test
Experience in memory timing & power characterization
Proficiency in Low-Power, Low-Voltage & Low-Leakage design practices
Experience in advanced geometries and understanding of different technologies (FDSOI, FinFet)
Experience with memory compilers is an advantage
Proficient in Cadence virtuoso schematic design, Spice simulators, Fast-Spice & mixed-signal simulators, High-Sigma analysis tools, Parasitic extraction & modeling, Memory characterization
This position is open to all candidates.
 
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