דרושים » חומרה » Hardware Engineer

Spearhead innovative silicon architecture for AI infrastructure, guiding board design from concept through to mass production.

Act as the technical decision-maker for the project and collaborate with cross-functional teams in mechanics, thermal, PCB layout, and software/RTL.

Define product specifications, develop electrical schematics, and guide component selection.

Conduct hands-on testing in a lab environment and drive the PCB bring-up, characterization, and debugging stages.

In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.

You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.

Responsibilities:
As a member of the Package Design team, you will:

Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing support.

Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.

Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.

Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.

Assist in developing and improving package design methodologies, flows, and best practices.

Contribute to debugging, issue resolution, and package bring‑up activities as needed.

Lead hands-on lab debugging to fix complex silicon performance, characterization, and yield issues. Use bench findings and board-probing data to give feedback directly to the architecture and design teams. Lead ASIC bring-up on validation boards, focusing heavily on SerDes, high-speed interfaces, and power/clock domains. Run characterization across PVT (Process, Voltage, Temperature) conditions and analyse large datasets to resolve performance bottlenecks and improve chip yield. Write and optimize clean Python code to automate lab equipment and test internal chip logic. Serve as the technical lead for complex hardware debug, defining validation methodologies, and advanced lab measurement techniques for the team.

As SIPI engineer youll be required to design and analyze high speed analog/digital signals for networking products, with emphasis on high speed signal and power analysis of ASIC, Package and PCB. Model/simulate/characterize high speed systems, including high speed I/Os, chip packages, printed circuit boards, and system interconnects. Overcome the challenges of ultra-high data rate and cutting-edge technology. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.

We are seeking a high-driven, results-oriented multidisciplinary orchestrator to act as the primary catalyst for our development infrastructure. In this role, you will operate at the critical intersection of product strategy, hardware engineering, and lab operations, serving as the connective tissue that aligns disparate teams under a unified goal. You will be responsible for driving cross-functional alignment across the organization, effectively managing stakeholders with differing ownership to ensure infrastructure roadmaps scale alongside product milestones. This position requires a self-starter comfortable pushing for success in ambiguous environments, where you will translate high-level strategy into the tactical execution of the physical and virtual ecosystems that power our development lifecycle.

Your Impact

You will own the end-to-end lifecycle of infrastructure projects, ensuring that our Sanity Test Beds and development environments are optimized to meet aggressive product launch timelines. By bridging the gap between engineering roadmaps and infrastructure requirements, you will serve as the engine that ensures our teams have the right resources at the right time, regardless of technical or organizational complexity.

Key Responsibilities

Strategic Orchestration & Alignment

Unified Roadmap Integration: Translate complex product development roadmaps into long-term infrastructure requirements, driving cross-functional alignment between silicon milestones and lab availability.
Stakeholder Management: Act as the primary liaison between hardware engineering, software development, procurement, and lab operations; navigate competing priorities among stakeholders with differing ownership to keep teams synchronized.
Ambiguity Management: Proactively identify project roadblocks and navigate ambiguous environments to push critical-path dependencies to resolution.
Operational Velocity: Drive continuous improvement in infrastructure processes, identifying and removing friction to increase overall engineering velocity.
Operational Oversight & Execution

Strategic Capacity Planning: Lead high-stakes capacity management efforts, forecasting needs for power, rack space, and compute resources to proactively eliminate infrastructure bottlenecks.
Lifecycle Ownership: Oversee the full lifecycle of infrastructure projects-from initial procurement and technical specification through deployment, validation, and transition to operational readiness.
Visibility & Reporting: Drive the development of dashboards and reporting mechanisms to provide real-time visibility into infrastructure health, ensuring data-driven decision-making across the organization.
Vendor & Asset Optimization: Partner with cross-functional leadership to manage technical specifications, equipment lead times, and hardware lifecycles, ensuring a high-performance, cost-effective infrastructure footprint.

You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.

Contribute to physical synthesis, place and route, optimization, and timing closure for complex VLSI designs.
Support design floor planning and implementation planning in collaboration with senior physical design engineers.
Analyze timing, congestion, power, area, and design-rule issues and help drive them toward closure.
Work with physical design verification flows, including LVS and DRC, to support clean implementation handoff.
Partner with cross-functional teams to debug implementation issues and improve backend flow quality.

Write and review micro-architecture specifications

Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements

Contribute to full chip integration, timing methodology, and analysis

Collaborate with verification engineers to resolve bugs and achieve coverage closure

Work with the physical design team to close timing and PnR issues

Support design methodology evolution and best practices

Perform debug, root-cause analysis, and post-silicon validation in the lab

You will lead sophisticated, multi-functional programs spanning silicon development, firmware, and system delivery, driving execution from initial concept through production. You will collaborate with engineering and operations teams to deliver high-quality solutions, craft effective processes, and ensure strategic alignment across the organization.

Specific Responsibilities include:

Driving end-to-end program execution for the Silicon One ASIC software ecosystem, including integration with industry-leading network operating systems.
Serving as a key interface for New Product Introduction (NPI) programs for next-generation Cisco Silicon One devices.
Leading cross-functional alignment across engineering teams in a globally distributed environment.
Owning program schedules, milestones, dependencies, risk management, and executive communications.
Partnering with software engineering leaders to ensure tight hardware/software co-development and integration.
Liaising with Cisco internal business units and customers to collect requirements and manage prioritization across competing stakeholder interests.
Driving accountability for outcomes while working through influence in environments with high ambiguity, rapid change, and ambitious timelines.

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab