דרושים » חשמל ואלקטרוניקה » Verification Engineer

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לפני 20 שעות
חברה חסויה
Location: Merkaz
Job Type: Full Time
We are looking for highly motivated engineers who love the challenges and the opportunity of a small company.
Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.
Requirements:
Sc in Electronics Engineering or Computer Science
10+ Years of industry experience in verification, full chip dev. cycle.
Experience with System Verilog and UVM methodology - MUST
Advantages:
M.Sc. in Electronics Engineering or Computer Science
Working experience with Formal verification
Scripting skills in Python/Perl/shell
Hands-on experience with two or more of the following :
PCIE (Gen5 and above).
DDR (v4 and above).
AMBA protocol family, (inc. AXI4+, ACE/CHI)
ARM core architecture.
This position is open to all candidates.
 
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חברה חסויה
Location:
Job Type: Full Time
We are looking for highly motivated engineers who love the challenges and the opportunity of a small company.
Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.
Requirements:
BSc in Electronics Engineering or Computer Science
10+ Years of industry experience in verification, full chip dev. cycle.
2+ years of experience in leading a team of engineers (including technical and personal mentoring, etc.)
Experience with System Verilog and UVM methodology - MUST
Advantages
M.Sc. in Electronics Engineering or Computer Science
Working experience with Formal verification
Scripting skills in Python/Perl/shell
Hands-on experience with two or more of the following :
PCIE (Gen5 and above).
DDR (v4 and above).
AMBA protocol family, (inc. AXI4+, ACE/CHI)
ARM core architecture.
This position is open to all candidates.
 
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20/05/2026
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time and Hybrid work
We are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Position location: in our Haifa or TLV offices, at least 2 working days at Haifa site (Hybrid model)
Responsibilities:
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.
Requirements:
B.Sc. in Electrical/Computer Engineering or equivalent.
5+ years of experience as a VLSI Verification Engineer.
Expertise in System-Verilog and UVM.
Strong software development skills and the ability to develop reusable verification components and utilities.
Strong organizational and planning skills, with the ability to prioritize and drive verification projects to completion.
Effective communicator with a structured, detail-oriented approach to problem-solving and collaboration.
Advantages:
Experience with Git, Python, code templating methods, and open-source verification workflows.
Familiarity with full-chip level aspects of VLSI verification (reset architecture and sequences, power domains and modes, etc.).
Experience in firmware verification, including emulation-based verification on FPGA.
Experience with formal verification or mixed-signal simulation.
This position is open to all candidates.
 
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26/05/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking to hire a talented Verification Engineer to join our VLSI group in Tel Aviv.
You will work alongside other talented engineers to develop our cutting-edge AI chips. If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities:
Collaborate with architecture and design teams to define and implement comprehensive testcases for NN processor and SoC blocks and flows.
Maintain, enhance, and scale the UVM‑based verification environment to support efficient and robust verification.
Own end‑to‑end verification of system flows to ensure the design is fully functional, correct, and meets performance expectations.
Drive root‑cause analysis and debug across RTL, testbench, and system layers to ensure high‑quality design closure.
Define, track, and close functional and performance coverage to guarantee verification completeness.
Continuously improve verification methodologies, automation, and workflows to increase productivity and coverage efficiency.
Requirements:
B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or a related field from a leading university.
3+ years of hands‑on experience in ASIC design or verification.
Strong knowledge of SystemVerilog and the UVM verification methodology.
Experience with SoC‑level verification is an advantage.
Excellent problem‑solving abilities and strong communication skills.
Proficient in written and spoken English and comfortable collaborating with a global team.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience with creating and using verification components and environments in standard verification methodology.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience in four or more System on a chip (SOC) cycles.
This position is open to all candidates.
 
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חברה חסויה
Location: Giv'atayim
Job Type: Full Time
We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.

Responsibilities
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches.
Work closely with the verification team to ensure the quality of the product.
Build and maintain a smart and scalable verification environment that ties into various systems.
Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design.
Requirements:
6+ years of verification experience, including hands-on experience building complex environments from scratch.
Advanced knowledge of verification flow, SOC architecture and design.
Expertise in verification languages such as SystemVerilog, UVM, Spaceman.
Knowledge of industry standard tools, including Verilog, Verilog simulator, and debug.
Clear understanding of constrained random verification process, functional coverage, code coverage, and assertion methodology and philosophy.
Bachelor degree in electrical engineering or computer science, or equivalent experience.
This position is open to all candidates.
 
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10/05/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
Required Senior Chip Design Verification Engineer
job requisition id
We have been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technology-and amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As an employee, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
Join us and become a pivotal part of our Networking Silicon engineering team in Tel Aviv, Israel. We are renowned for developing the industry's top high-speed communication devices, known for their outstanding efficiency and minimal latency. This role offers an outstanding opportunity to be involved in groundbreaking projects, collaborating with versatile experts to foster innovation and excellence. As a Senior Chip Design Verification Engineer, you will be immersed in a dynamic and encouraging environment where your efforts will have a meaningful impact.
What you'll be doing:
Play a crucial role in developing our next-generation chip controller.
Engage in building and verification tasks within a challenging, multi-disciplinary context.
Collaborate closely with cross-functional teams to advance our networking and GPU networking chips and systems.
Drive the implementation of sophisticated verification environments to ensure flawless functionality.
Mentor and guide junior engineers, encouraging a collaborative and inclusive team atmosphere.
Requirements:
What we need to see:
B.Sc. or M.Sc. in Computer Engineering, Electrical Engineering, or Communication Engineering, or equivalent experience.
A minimum of 5 years of proven experience in ASIC Verification.
High proficiency in English.
Demonstrated ability to work well within a team, exhibiting strong communication and interpersonal skills.
A proactive and ambitious approach, with strong attention to detail and a dedication to excellence.
Background in Specman - advantage
Knowledge in industry Standard Protocol such as I2C, SPI, AMBA and RMII - advantage.
Knowledge in HDL (Verilog/VHDL) - advantage.
This position is open to all candidates.
 
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11/05/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a Software Engineer or Computer Scientist for our Software Formal Verification team! This is an exciting opportunity to join a unique team dealing with cutting-edge Formal Verification technology for both software and hardware. Supporting our Switch, NIC, and GPU technologies, we research and use state-of-the-art formal verification tools and methodologies to mathematically prove the correctness of both software and hardware. You will be joining a growing team, using both in-house and third-party technologies that keep developing, and assist in defining new methodologies. As part of this team, you'll enjoy a versatile work environment that is educational, dynamic, and ambitious.
What you'll be doing:
In this position, you will use formal verification tools and methods to mathematically prove the correctness of complicated logic problems
Help develop our Software Formal Verification methodologies and tools
You will work on ambitious designs along with our Firmware and Software teams and take part in developing the next generation of our core technology.
Requirements:
BSc in Computer Engineering/Computer Science/Mathematics or equivalent
4+ years of experience in Software
Excellent analytical, logical reasoning, and problem-solving skills
Strong communication and interpersonal skills
Fluent in English
Ways to stand out from the crowd:
Background in architecture simulators
Experience in firmware / embedded systems
Experience in Formal Verification in software
Hands-on experience applying AI in a professional environment.
This position is open to all candidates.
 
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Location: Haifa
Job Type: Full Time
We are seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments.
This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects/designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks/functions of commonly used logic, to be later used off the shelf.
Requirements:
BSc in electrical engineering, computer engineering, or computer science
Passion for the field of Formal Verification
5+ years of experience in Formal Verification
Experience coding system-verilog hardware description language
Experience with scripting languages (e.g. python, tcl)
Strong analytical and problem solving skills
Ability to work independently and in a team-oriented environment.
This position is open to all candidates.
 
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06/05/2026
חברה חסויה
Location: Caesarea
Job Type: Full Time
We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.
Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.
Requirements:
5+ years of experience as a Verification Engineer.
B.Sc./M.Sc. in Electrical/Computer Engineering from a leading university.
Strong knowledge of System Verilog and UVM methodology.
Experience in pre-silicon functional unit level/cluster/full chip verification.
Experience in verification of packet processing/Ethernet/RDMA/InfiniBand
Familiarity with SoC architecture, CPU subsystems, and multi-core designs.
Advantages
Knowledge of formal verification and emulation/FPGA prototyping.
Exposure to AI/Networking workloads and performance validation.
This position is open to all candidates.
 
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11/05/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a Formal Verification Engineer for our Networking team!
This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking Switch technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our Switch team delivers world class Bridge and router solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver smart and high bandwidth multi port switches. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
What you'll be doing:
In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.
Requirements:
BSc in Electrical/Computer Engineering or MSc in Mathematics.
Excellent analytical, logical reasoning and problem-solving skills.
Strong debugging and analytical skills.
Strong communication and interpersonal skills are required.
Ways to stand out from the crowd:
Formal verification work experience.
Knowledge of digital logic.
This position is open to all candidates.
 
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