דרושים » חשמל ואלקטרוניקה » SW Engineering Manager - Performance Modeling

Required Software Engineer, CPU Performance Modeling, Cloud
About the job
Our software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to our needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.
In this role, you will work with System teams and the CPU Architecture team to develop an understanding of the Central Processing Unit (CPU), System on a Chip (SoC), performance metrics, benchmarks/measuring tools, and available optimization knobs. You will define methods and technologies to model CPU performance at different accuracy levels by supporting architectural explorations and decision making. You will correlate performance projections with measured post-silicon data.
Responsibilities
Write product or system development code.
Design, develop, test, deploy, maintain, and improve Central Processing Unit (CPU) software modeling and other software tools.
Manage project priorities, deadlines, and deliverables.
Collaborate with hardware and software CPU Architecture teams, SoC performance modeling team, and other Software teams.

We are seeking an experienced and highly motivated C++ Software Engineer to join the Compiler team of our Network Technology R&D organization, contributing directly to the evolution of next-generation networking products.
Meet the Team:
Our team builds firmware, SDKs, simulators, and compilers for the Silicon One architecture - the industrys first routing and switching silicon architecture unifying networking across all layers. You will work on pioneering technology that powers the future of the Internet.
You will be part of a global team working on the newest generation, which will be integrated across the entire portfolio of our devices.
You will collaborate with worldwide distributed R&D centers, gaining exposure to some of the most talented engineers in the networking industry. We look for people who love technology and engineering-people who thrive on innovation, continuous learning, and challenging whats possible.
Your Impact
Design, implement, and test a state-of-the-art optimizing compiler for Silicon One
Evaluate and optimize code performance, including debugging, code generation improvements, and pipeline analysis
Develop, optimize, and enhance the compiler backend to fully leverage cutting-edge hardware capabilities
Solve complex resource management challenges across hardware pipelines
Design and implement new P4 language features that empower network application developers
Build and maintain the compiler toolchain for custom networking applications
Contribute to libraries, analysis tools, and supporting infrastructure
Collaborate with cross-functional hardware and software teams
Work closely with ASIC engineers on next-generation IC design, influencing hardware through compiler insights prior to tape-out.

We are looking for a talented Code Generation and Optimization Expert. We are looking for a self-independent engineer to join the team that builds the software infrastructure for accelerating the system in large scale compute environments like data centers and HPC using new CPU core technology. Working on the cutting edge and future ready systems. We work in a development culture that is diverse, flexible and challenging. For persons looking to make an impact and influence the future of computing with personal growth options.

The team is developing core components in the automated optimization process that adapts our unique hardware architecture to run any HPC & AI applications, with little to no code modifications required. By using iterative rounds of telemetry and optimization, our compiler is able to intelligently adapt our accelerator into a workload-specific ASIC, at runtime.

We are seeking a talented Code Generation and Optimization Expert to join our bleeding-edge team in Israel. In this high-visibility, hands-on role, you will play a pivotal part in building our next-generation runtime compiler.

Responsibilities
Design and maintain the distributed and heterogeneous executable that is generated by our compiler stack.
Using the MLIR framework, transform high level compiler outputs into hardware-specific binary images, memory mappings, execution parameters, resource allocation, region grouping, and cross-domain coordination for distributed systems.
Design and maintain the API layer (libRT.a) connecting compiler-generated code with runtime services, ensuring seamless integration across different execution domains.
Collaborate closely with hardware, architecture, verification and other compiler teams to align software with hardware requirements and behavior.

We are looking for a highly experienced Real-Time C++ Team Leader who embodies ambition and positivity.
Someone who can passionately take ownership of their responsibilities, leading a talented team while collaborating effectively with remote and on-site teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.
The Real-Time C++ component is at the core of our Quantum Orchestration Platform - it serves as the driver for the Pulse Processing Unit (PPU), our proprietary VLSI-based engine. This component is responsible for preparing, loading, and launching the execution of quantum-computing workloads, operating at extreme performance levels to maximize hardware utilization and minimize software overhead.
Responsibilities
Lead and grow a team of real-time C++ engineers, fostering technical excellence, collaboration, and professional development.
Own the architecture and development of the real-time C++ layer that drives the Pulse Processing Unit (PPU), our company's proprietary VLSI-based processor.
Design and implement high-performance software for preparing, loading, and launching quantum-computing workloads with minimal latency and maximal hardware utilization.
Drive relentless optimization of the software stack to minimize SW overhead in the critical path, ensuring the hardware operates at peak throughput.
Collaborate closely with VLSI, compiler, and architecture teams to ensure seamless software-hardware integration across the quantum control stack.
Define and uphold engineering standards, code quality practices, and performance benchmarking methodologies for the team.
Contribute hands-on to the codebase - designing, reviewing, debugging, and profiling performance-critical code paths.
Participate in cross-team technical planning, roadmap definition, and alignment with product and customer needs.

As a Wireless Firmware Architect you will focus on defining technical direction, conducting research and analysis, and providing architectural guidance for our Bluetooth embedded solutions.

The position emphasizes wireless protocol design and simulations, software architecture definition, technical planning, proof-of-concept development and performance optimizations.

Responsibilities:
Define comprehensive software architecture for our Bluetooth embedded solutions.
Establish firmware architectural guidelines and principles.
Support development teams with architectural guidance and consultation.
Integrate performance and power analysis requirements into architectural frameworks.
Create technical demonstrations to support architectural decision-making.
Monitor and analyze hardware implementations to ensure alignment with software architectural requirements.
Evaluate hardware design decisions and their impact on firmware architecture.
Collaborate with hardware teams to provide architectural input and recommendations.
Design and develop proof of concept (PoC) projects to validate architectural approaches.
Research and prototype emerging wireless technologies and methodologies.
Evaluate feasibility of new technologies and integration approaches.
Design and develop wireless protocol simulation frameworks, develop intelligent simulation environments for protocol validation and optimization.
Analyze new standards and specifications for architectural implications.
Track industry trends and emerging wireless technologies.

we are a leading semiconductor design center, developing SoCs, microcontrollers, and security hardware solutions for tier-1 customers in the computing and server space. As a self-contained R&D center - spanning architecture, chip design, software, and system engineering - we work closely with major US-based OEMs to deliver innovative, semi-custom silicon solutions. We are now extending our portfolio into AI acceleration, developing a next-generation NPU platform aimed at efficient, real-world AI deployment.
?Shape the Future of AI at the Silicon Level We are looking for a visionary Senior Technical Manager to build and lead our AI software stack for our next-generation NPU platform This is a rare opportunity to own the full software layer - from compiler infrastructure to Developer ecosystem - and make a lasting impact on how AI runs on silicon. What You'll Do; Build and lead a highly skilled AI software & algorithms engineering team, establishing engineering standards, development processes, and technical direction Define the end-to-end stack - compiler, runtime, Kernel libraries, and SDK - enabling efficient AI deployment on our NPU Drive AI compiler development using technologies like MLIR, TVM, LLVM or similar infrastructures to translate PyTorch/TensorFlow models into optimized NPU execution Champion model optimization - quantization, pruning, and hardware-aware techniques for maximum performance and power efficiency on the accelerator. Runtime, Drivers, and Firmware Integration - scheduling, memory management, and low-level software for AI workloads on-chip AI Kernel Libraries - Guide the development of highly optimized neural network Kernel libraries and performance-critical primitives tailored to the architecture of the NPU. Developer Ecosystem - Define and deliver the SDK, APIs, and development tools that allow internal teams and external developers to deploy AI models easily on the platform. Cross-Functional Architecture Collaboration - Work closely with silicon architecture and hardware design teams to ensure optimal hardware-software co-design, providing feedback on architecture, performance bottlenecks, and future ISA requirements.

We are seeking an experienced and highly skilled Software Engineer to join our Runtime Software group. In this role, you will drive the development of the full software stack and architecture behind our revolutionary coprocessor. You will be challenged to deliver high-performance, system-wide solutions, requiring a deep understanding of complex architectural trade-offs and distributed systems.

As a core team member, you will design and implement infrastructure that enables our unique hardware to accelerate diverse applications at scale. You will collaborate across disciplines - working with hardware engineers, compiler developers, and system architects - to optimize execution in a massive, multi-process, and multi-threaded environment.

Responsibilities
Design and implement next-generation runtime architectures and infrastructures to support evolving product requirements.
Develop environments for the acceleration of massively parallel applications, managing complex process and thread lifecycles.
Define development scopes and roadmaps to ensure the successful delivery of robust software features.
Partner with hardware and compiler teams to bridge the gap between silicon capabilities and software performance.

We are looking for a SoC / IP Architect to shape the next revolution in electronics!
Responsibilities
Define and design architecture: Create the overall SoC/IP architecture based on product and customer requirements and define detailed technical specifications.
Collaborate with cross-functional teams: Work with a variety of teams, including logic design, verification, firmware architecture and development teams, and physical design, to ensure successful execution.
Lead technical discussions and architectural reviews, guiding design and verification teams to deliver scalable, high-quality implementations.
System-level integration: Ensure seamless hardware-software co-design by working on aspects like control paths, interrupt schemes, and debug infrastructure.
Drive architectural decisions that optimize scalability, and future readiness for next-generation applications.

our SW group is looking for a strong system-level team leader to join our SW IM team and take part in developing complex, high-performance software systems that drive multidisciplinary semiconductor metrology tools.
In this role, you will lead a team while providing strong technical direction across the full software stack, from low-level hardware interfaces (motion controllers, optical and laser subsystems, sensors, cameras, etc.), through sequence control, and up to UI and reporting layers. The role is expected to remain hands-on mainly through guiding architecture and design decisions, mentoring and training team members, driving technical quality, and helping the team solve complex system-level challenges.
You will operate in a highly technical, system-oriented environment that requires deep understanding of software-hardware interaction, strong analytical thinking, and close collaboration with system engineers, QA, and other software teams. The role requires end-to-end ownership of team deliveries, from design through implementation and delivery.
This position is ideal for a leader who combines strong engineering fundamentals, system-level thinking, people leadership, and technical mentorship, and is passionate about building robust, scalable systems in complex multidisciplinary environments.
Responsibilities:
Lead a team of 4-7 software engineers
Manage team capacity, planning, and execution to meet project goals
Provide technical direction and architectural guidance
Mentor, train, and grow team members
Drive high-quality software development and engineering standards
Own end-to-end team deliveries
Collaborate with system engineers, QA, and other SW teams
Serve as focal point for cross-team communication
Contribute to organizational process and tool improvements

we are looking for a Senior SW Engineer.
Job Description:
Join a multi-disciplinary team of experts operating at the core of Speedatas software stack
Lead the design and implementation of highly efficient algorithms that maximize our performance
Develop time-critical Python components that translate database operations to performant, hardware-optimized C++
Co-design the next generation of our architecture alongside Hardware & Software engineering leads
Research state-of-the-art algorithms and techniques for data analytics and hardware acceleration
Fly high with the SW, and dive in for a byte of the HW