דרושים » הנדסה » Senior VLSI Design Engineer

We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.

Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.

We are seeking a CAD Engineer to join the Physical Design team.

You'll be joining our Physical Design team within us, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Physical Design team within us is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Your Impact
You'll be part of the team, which is at the heart of our software and ASIC design efforts.

You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

We are looking for a hands-on, experienced Physical Design Engineer to join us and help define and implement next-generation AI SoC in an advanced technology node

You will play a key role in building and leading our physical design team, developing flows and methodologies, and driving the full RTL-to-GDSII implementation and signoff for one of the most advanced SoCs in the industry.
What Youll Do

Take part in shaping methodology and best practices in advanced technologies

Drive end-to-end implementation: synthesis, P&R, timing closure, and signoff

Collaborate closely with architecture and design teams on timing, floorplaning, partitioning, and power specification

Define and optimize static timing constraints, area, and power goals at block and top levels

Take part in flow development and automation to improve efficiency and quality of results

You'll be joining the Israeli team which is the core center of our SW and ASIC design. You'll be part of the group driving our groundbreaking next-generation network devices. Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs. Join a team of dedicated engineers with a proven track-record at delivering breakthrough products. Our R&D center is outstanding - hosting all silicon HW and SW development teams inside one site. We are transforming the industry and building a new AI/ML Networks, as well as providing a unified, programmable silicon architecture that is the foundation of all our future routing products. Our devices are crafted to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed (50+ Terabits per second) without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

We are a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine! You have a unique opportunity to join the core center of our SW development and work with us to design and deliver breakthrough technologies

What You'll Do:

You'll be joining our Physical Design team, which is at the center of the silicon development. Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.

We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

Join the Front-End Design team, at the core of our development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.

Your Impact:

Review micro-architecture specifications.

Implement Verification environment UVM based.

Collaborate with Design engineers to resolve bugs and achieve coverage closure.

Work with the firmware/Lab teams to verify chip flows.

Perform debug, root-cause analysis, and post-silicon validation in the lab.

The company`s Factory Applications group is looking for a highly motivated, energetic, and self-driven engineer to join our Silicon Photonics product team. You will work on projects collaboratively with cross-functional teams across the company, as well as develop imaginative, thorough, and practical application solutions separately.

In this position, we are looking for someone who can leverage their experience into a multifaceted technical leadership role - being an expert in our products for outbound activities, and representing the broad user base for inbound new product development.

In this position you will work at our office in Haifa, Israel.

Responsibilities:
Leading member of product development teams with engineering, representing the broad user base -defining use cases and requirements, and performing post-implementation validation. Responsibility is to ensure we are implementing the right things to meet market expectations with competitive solutions.
Participate in key-design-ins acting as expert consultant, ensuring technical success, at times taking on the role of project technical leader.
Provide expert guidance to our field applications and direct customers in development of successful test solutions.
Develop and deliver technical marketing presentations with clear and effective messaging.
Co-develop user documentation and training for new products and features.
Continually develop deep expert knowledge of our products and use models.
Continually develop knowledge of semiconductor/Silicon Photonics test requirements and trends.
Develop strong relationships with worldwide account teams and key customers.
Develop knowledge and expertise on semiconductor device testing.
Develop knowledge and expertise on Automated Test Equipment (ATE) - specifically the UltraFLEXplus family of our testers - with a focus on our Silicon Photonics and Software product area, with addition of Digital, Serial and DC products as projects require.
Support customers on tester operation and capability.

Your Impact:

Review micro-architecture specifications.

Supervise verification team members and provide professional guidance.

Implement Verification environment UVM based.

Collaborate with Design engineers to resolve bugs and achieve coverage closure.

Work with the firmware/Lab teams to verify chip flows.

Perform debug, root-cause analysis, and post-silicon validation in the lab.

Your Impact:
Write and review micro-architecture specifications.
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements.
Contribute to full chip integration, timing methodology, and analysis.
Collaborate with verification engineers to resolve bugs and achieve coverage closure.
Work with the physical design team to close timing and PnR issues.
Support design methodology evolution and best practices.
Perform debug, root-cause analysis, and post-silicon validation in the lab.