We invite you to join the DP QA department responsible for high end enterprise security solutions. Our cutting edge security platforms simplify operations while ensuring resilience, efficiency, and SLA adherence.

In this role, you will take an active part in mastering our Next Generation Cyber Security products, with a strong emphasis on automation, quality engineering, and the adoption of AI driven testing methodologies.

You will work in an Agile Scrum environment within a dynamic, fast growing, and highly innovative team.

What will you do?
Planning, design, development, reporting, and analysis of manual and automation tests.
End to end testing of various DP features and components.
Building and maintaining automation frameworks for complex networking and security environments.
Utilizing AI powered tools to improve test coverage, defect detection, and root cause analysis.
Developing test insights using AI/ML models for anomaly detection and optimization of regression cycles.
Collaborating with development, QA, and data teams to integrate AI assisted automation into CI/CD pipelines.
Participating in Agile processes, contributing to test strategy and continuous quality improvement.

The Design for Test (DFT) team is part of the design group, which focuses on logic design, RTL development, and running verification tests. Their main role is to design test structures embedded within the chip to ensure proper functionality after manufacturing. The goal is to detect potential manufacturing defects with maximum efficiency and filter out faulty units before they reach the market.

The ideal candidate is friendly, social, easygoing, with a good sense of humor, and has the ability to learn independently. They should be located in central\north Israel (Tel-Aviv\Caesarea). Strong independent work skills and job stability are important.



What You'll Do

Work in a small, agile team with an intimate atmosphere that offers direct mentoring and broad professional growth. Insert DFT logic, perform synthesis, and run Automatic Test Pattern Generation (ATPG) to ensure hardware testability. Execute Gate Level Simulations, timing checks, and DRC checks to maintain rigorous design integrity and performance standards. Run regressions and perform deep-dive debugging on simulation failures as part of the core verification process.