דרושים » הנדסה » Senior HW architect

Requirements:
BSc / MSc / PhD in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in VLSI / ASIC design, chip architecture, or micro-architecture of complex blocks.
Proven experience leading or managing a small team of designers, verification engineers, or HW architects.
Ability to take an idea into implementation.
Strong background in high-speed networking systems, such as:
o Ethernet Switches
o NPUs
o NICs
o Traffic Managers
o Fabric Switches
o High-performance processors
Skills
What Were Looking For
Strong technical leadership with the ability to drive architectural vision.
Excellent written and verbal communication skills in English.
Outstanding collaboration and teamwork skills across disciplines and organizational levels.
Independent, self-driven, and comfortable taking full ownership of complex challenges.
Passion for innovation and cutting-edge networking technologies.
Highly motivated with a proactive, can-do mindset.

Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Solid understanding of general purpose CPU micro-architecture, including load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory technologies and memory controllers.
Ability to make trade-offs between power, performance and area to meet the requirements of the product.
Hand-on experience with high power-efficient CPU on chip interconnect, coherent fabric, memory controllers.
At least 8 years experience in architecture in one of the leading CPU companies
Experience modeling microprocessors using higher-level languages, like C/C++.
DESIRED
Co-operate and communicate well with the architecture and design teams.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Minimum of 10 years of proven design experience in complex processor projects.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to US, Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills
MINIMAL REQUIREMENTS
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
Ownership of the overall verification methodology for a CPU project.

Requirements:
Minimum Skills And Experience
Experience with ASIC FE logic design. RTL coding, FE tools and signoff.
Experience in complex design (data-path or control-path)
Required Skills And Experience
BS/MS in Electrical and/or Computer Engineering with 8 to 10 years of experience.
Knowledge and experience in CPU or micro-controller designs (multi pipeline)
Processor system knowledge includes basic understanding of SoC systems as well as operating system software is a plus.
Great communication & teamwork skills.
Minimum Qualifications
Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field.
References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Requirements:
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
At least 20 years of experience in one of the leading CPU companies
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
QUALIFICATIONS
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
MSc or BSc in computer science/EE or area related to computer architecture, or equivalent research experience in industry
At least 7 years of relevant research and development experience in industry and academia in the following areas:
Computer architectures: instruction set architecture, microarchitecture, cache sub-system, memory sub-system, NOC, interconnect
Workload characterization and analytical model generation
System Modelling and emulation of HW.
Simulation of Software workloads and Software applications on HW simulator
Ability to provide innovation and global vision throughout the company
Excellent communication, presentation and reporting skills
Experience working with highly technical teams and communicating to non-technical partners.
Excellent oral and written English.

Requirements:
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Good understanding of CPU design methodology
Excellent verbal and written communication skills.
CPU related Experience in one of the leading CPU companies or in academia.
Willing to relocate to China for extended period.
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Experience modeling microprocessors using higher-level languages, like C/C++.

Requirements:
BSc or higher degree in Computer Science/Engineering or related discipline from a leading university. (Alternatively, exceptional proven track record in similar tasks)
5+ years of experience in one or more of following disciplines: definition of CPU architectural features, HW/SW co-design (or SW defined HW), Low level performance profiling and optimization of SW with exposure to CPU ISA.
Fluent spoken and written English
Behavioral skills: Team player. Although this is not for a manager position, we require interpersonal skills needed to lead partners and colleagues towards achieving a technical goal

Advantageous qualifications:
Familiarity with dense compute workloads and analysis (e.g., AI, HPC, financial, etc.)
Familiarity with Vector Architectures.

Requirements:
Four or more years of experience in one or more of the following roles in the memory cluster of an Out of Order CPUs:
Architecture or micro-architecture definition.
Performance modeling and studies.
RTL implementation.
Verification of Multithreading.
Education: Academic degree in Computer Engineering or Computer Science
Advantages:
Knowledge and experience in memory ordering architecture.
HW or SW Experience in inter-thread synchronization.
Knowledge of the arm Instruction Set Architecture.
Skills
Good verbal English skills.
Good interpersonal skills
Team player.

Requirements:
What do we want to see?
B.Sc. degree in computer science, computer engineering, or a closely related field
Proficiency in one or more low-level programming languages: C / C++
3+ years of experience in object-oriented software development (OOD)
Ways to stand out from the crowd:
M.Sc. or Ph.D. degree
Hands-on experience in parallel programming or distributed application development (MPI / OpenMP / SHMEM)
Experience with code optimizations (I/O, data structure, communication patterns, vectorization) and profiling
Experience in development and utilization of innovative algorithms and data-structures to optimize code performance
Experience in development and deployment of AI models and, with string proficiency in Python programming
Experience in developing and contributing to large codebases.