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Location: Hod Hasharon
Job Type: Full Time
our company, Huaweis Tel Aviv Research and Innovation Center, is looking for an experienced hands-on software engineer and compiler technology expert to join our Future-Computing-Infrastructure expert group. The group designs and develops technologies for the next-generation data center aimed at accelerating AI workloads for a unique HW, optimizing compute resource utilization and reducing data-center costs. Our projects involve hardware and software architecture co-design. They require high-level system understanding, creativity and innovative thinking.
If you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!
What will you be doing?
Complex static code analysis to determine possible bottlenecks and time-consuming operations within the code of AI model for inference
Architecture, design and implementation of compilation passes, compiling high-level languages to a unique HW
Take initiative to solve technical and business problems
Collaborate with other development and product teams in our company and in China to ensure the successful implementation and delivery of a solution.
Requirements:
B.Sc. in Computer Engineering / Computer Science or equivalent
At least 5 years experience in implementation and design of SW / SW+HW systems (mainly in C / C++)
Hands on experience with compilers design, architecture and implementation
At least 3 years experience using LLVM / MLIR
At least 3 years proven experience working with GPU instruction set architecture
At least 3 years proven experience using compilers for optimizing given AI models to run on GPU
System view, together with profound understanding of related technologies
Hands-on system design and PoC bring-up experience
Excellent communications skills and ability to work as part of an international team
Innovation, fast learning skills
Ways to stand out from the crowd:
M.Sc. or Ph.D. degree with expertise in fields related to compilation / static analysis / AI model optimizations
Experience in Triton compilation
Experience in working with Torch Inductor
Proven experience in optimizing applications performance
Proficiency in C++ programming language
Understanding in multiprocessing and multithreaded code.
This position is open to all candidates.
 
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Haifa
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will be part of a team developing application-specific integrated circuits (asics) used to accelerate networking in data centers. you will have multiple responsibilities in areas such as project definition, design, and implementation. you will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.you will also be responsible for performance analysis for a networking stack using your knowledge.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud. our end users, cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead an asic subsystem.
understand how it interacts with software and other asic subsystems to implement data center networks.
define hardware/software interfaces. write micro architecture and design specifications.
define efficient micro-architecture and block partitioning/interfaces and flows.
collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience architecting networking asics from specification to production.
experience developing register-transfer level (rtl) for asic subsystems.
experience with cross-functional engagement in micro-architecture, design, verification, logic synthesis, and timing closure.
preferred qualifications:
experience working with software teams optimizing the hardware/software interface.
experience working with design networking like: remote direct memory access (rdma) or packet processing and system design principles for low latency, high throughput, security, and reliability.
experience architecting networking switches, end points, and hardware offloads.
experience in transmission control protocol (tcp), ip, ethernet, peripheral component interconnect express (pcie) and dynamic random access memory (dram) including network on chip ( NOC ) principles and protocols (e.g., axi, ace, and chi).
understanding of packet classification, processing, queuing, scheduling, switching, traffic conditioning, and telemetry.
proficiency in procedural programming language (e.g., C ++, Python, go).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Haifa
Job Type: Full Time
about the job
our company's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. our products need to handle information at massive scale, and extend well beyond web search. we're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data Storage, security, artificial intelligence, Natural Language Processing, UI design and mobile; the list goes on and is growing every day. as a software engineer, you will work on a specific project critical to our companys needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. we need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the Full-Stack as we continue to push technology forward.
in our company search, we're reimagining what it means to search for information - any way and anywhere. to do that, we need to solve complex engineering challenges and expand our infrastructure, while maintaining a universally accessible and useful experience that people around the world rely on. in joining the search team, you'll have an opportunity to make an impact on billions of people globally.
responsibilities
create new features and transition them into stable, production-ready systems for the windows our company app.
review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).
triage product or system issues and debug/track/resolve by analyzing the sources of issues and the impact on hardware, network, or service operations and quality.
partner closely with product managers, UX designers, and others to define technical requirements and drive the product roadmap forward.
Requirements:
minimum qualifications:
bachelors degree or equivalent practical experience.
1 year of experience with software development in one or more programming languages (e.g., Python, C, C ++, JAVA, JavaScript ).
1 year of experience with data structures and algorithms.
preferred qualifications:
master's degree in Computer Science or a related technical field.
1 year of experience with C ++ or typescript.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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חברה חסויה
Location: Haifa
Job Type: Full Time
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
with your technical expertise you will manage project priorities, deadlines, and deliverables. you will design, develop, TEST, deploy, maintain, and enhance software solutions.the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are  cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
create software solutions that improve the hardware post-silicon testing process through automation. this includes, but is not limited to, developing and maintaining an automatic TEST equipment (ate) program development infrastructure for both production and development environments.
propose, design and implement software automation that directly addresses bottlenecks in today's post-silicon TEST flow, from design for testing (dft) to ate.
review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).
contribute to existing documentation or educational content and adapt content based on product/program updates and user feedback.
triage product or system issues and debug/track/resolve by analyzing the sources of issues and the impact on hardware, network, or service operations and quality.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
5 years of industry experience with high performance, systems, and debugging.
5 years of experience in ate tools, flows and methodologies.
experience in code and system health, diagnosis and resolution, and software TEST engineering.
experience in ate TEST development, from dft/design verification (dv) to ate (e.g., reset, automatic TEST pattern generation (atpg), memory built-in self TEST (mbist), or functional content development to ate patterns).
preferred qualifications:
experience in ate TEST method library development taking ate low level drivers and developing automated solutions.
understanding of object oriented programming and functional programming.
excellent software skills and design practices.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
we're the driving team behind groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhsic hardware description language (vhdl)), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience architecting networking asics from specification to production or equivalent experience.
experience developing rtl for asic subsystems.
experience in micro-architecture, design, verification, logic synthesis, and timing closure.
preferred qualifications:
experience working with design networking: remote direct memory access (rdma) or packet processing and system design principles for low latency, high throughput, security, and reliability.
experience architecting networking switches, end points, and hardware offloads.
experience working with software teams optimizing the hardware/software interface.
experience in a procedural programming language (e.g., C ++, Python, go).
knowledge of tcp, ip, ethernet, pcie and dram.
familiarity with network on chip ( NOC ) principles and protocols (axi, ace, and chi).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are , cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
utilize performance and power models from the architecture team, as well as lab measurements, to validate and tune performance against established goals.
design and build tests to verify that the SOC design meets those goals.
develop and implement advanced technologies for running benchmark representations on pre-silicon environments.
analyze complex problems, identify core design weaknesses, and drive the resolution of performance issues in both pre- and post-silicon environments.
develop performance measurement frameworks, including key performance indicators (kpis), to produce regular reports and dashboards that support stakeholder decision-making.
Requirements:
minimum qualifications:
bachelor's degree in Computer Science, computer engineering, or electrical engineering, or equivalent experience.
8 years of experience in SOC or central processing unit (cpu) performance and power modeling, analysis, and debugging.
experience with computer architecture, focusing in the areas like interconnects, traffic quality of service (qos), distributed caches, and i/o flows.
experience in programming languages such as C, C ++, or similar.
experience in identifying, troubleshooting, and solving performance problems.
preferred qualifications:
experience with hardware description languages like verilog or systemverilog.
experience in one or more functional areas, such as coherent fabrics (e.g., amba chi/axi), memory controllers (e.g., lpddr5, ddr5), or i/o controllers (e.g., pcie, cxl).
experience in productizing features that enhance the performance or power characteristics of a design.
experience in building fast, accurate SOC /cpu performance models in C ++.
experience in pre-silicon and post-silicon analysis and debugging.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Haifa
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
collaborate with architecture, design, and verification teams to develop new product bring-up, validation, characterization, and qualification strategies, manufacturing TEST solutions for new high performance computing (hpc) products in advanced process technologies.
verify TEST solutions on pre-silicon models (simulation or emulation) and develop ate TEST modules, dc tests, binning, production flows, and characterization flows.
develop and validate TEST programs on ate platforms for new product integration (npi) in preparation for high volume manufacturing (hvm), working with ate vendors.
support product sustainability, including volume data analysis of screening and characterization data, TEST time and yield improvements, TEST escapees and return merchandise authorizations (rmas) assessments, failure localization, containment measure implementation, and partnership with design manufacturing, quality, and reliability teams to root cause and implement corrective actions.
develop tools, flows, and methodologies to continuously improve and automate the testing.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in design, TEST, manufacturing, or process engineering.
experience in pre-silicon validation, TEST content generation, ate program development, and post-silicon enabling from npi through hvm.
experience in asic TEST methodologies (e.g., mbist, atpg, dft, serdes, and sensors).
experience in Python, JAVA, C #, or C / C ++, and advantest or teradyne ate platforms.
preferred qualifications:
experience in creating end-to-end manufacturing TEST strategies for pcba and systems that cover structural through functional and system tests.
experience in ate hardware design and proliferation such as load boards/probe cards, handler kits, sockets, and thermal control solutions.
experience in developing or integrating manufacturing TEST hardware using electrical and thermo-mechanical components.
experience in developing automations for pre-silicon verification and post-silicon TEST -generation/ TEST -program domains.
experience with cpu/gpu SOC architecture, design, validation, and debug.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
lead an asic subsystem and understand how it interacts with software and other asic subsystems to implement groundbreaking data center networks.
define high-performance hardware/software interfaces. write micro architecture and design specifications.
define efficient micro-architecture and block partitioning/interfaces and flows.
implement designs in systemverilog.
collaborate with software, verification, and physical design stakeholders to ensure the designs are complete and correct.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience architecting networking asics from specification to production.
experience developing rtl for asic subsystems.
experience in micro-architecture, design, verification, logic synthesis, and timing closure.
preferred qualifications:
experience architecting networking switches, end points, and hardware offloads.
experience working with design networking like remote direct memory access (rdma) or packet processing and system design principles for low latency, high throughput, security, and reliability.
experience working with software teams optimizing the hardware/software interface.
experience in tcp, ip, ethernet, pcie, dram, network on chip ( NOC ) principles and protocols.
experience in a procedural programming language (e.g., C ++, Python, go).
understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8592849
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.as a design & power methodology team manager within the server chip design team, you will be responsible of managing and leading design and power methodologies from ip to SOC, pre and post silicon. you will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.you will work closely with cad vendors and internal teams to develop lead design and power methodology and execution.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
manage a team of tech leads and designers. develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
lead flow and methodology development and assimilation across multiple groups. work closely with cad tool providers as well as internal cad teams.
plan, execute, track progress, assure quality, and report status.
work closely with internal customers and support multiple activities and deliverables.
drive design methodologies such as design construction, cdc, rdc, sdc. drive power at: ip and SOC rtl/gate level optimization, estimation, correlation.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in rtl design cycle ip and SOC.
8 years of experience in team management.
experience with design methodologies, structural checks, and power estimation/optimization.
preferred qualifications:
experience with synthesis techniques to optimize register-transfer level (rtl) code, performance and power as well as low-power design techniques.
experience with a scripting language like Python or PERL.
experience with design for TEST and its impact on design and physical design.
knowledge of ip and SOC architecture.
knowledge of physical design techniques: sdc, synthesis, emir, etc.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8592897
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25/03/2026
Location: Haifa
Job Type: Full Time
As an ML Software Engineer with a focus on low-level and CUDA-based optimizations, you will play a key role in shaping the design, performance, and scalability of machine learning inference systems. Youll work on deeply technical challenges at the intersection of GPU acceleration, systems architecture, and ML deployment.
Your expertise in CUDA, C/C++, and performance tuning will be crucial in enhancing runtime efficiency across heterogeneous computing environments. Youll collaborate with designers, researchers, and backend engineers to build production-grade ML pipelines that are optimized for latency, throughput, and memory use, contributing directly to the infrastructure powering next-generation AI products.This role is ideal for an engineer with strong systems-level thinking, deep familiarity with GPU internals, and a passion for pushing the boundaries of performance and efficiency in machine learning infrastructure.

Responsibilities
Design and implement highly optimized GPU-accelerated ML inference systems using CUDA and low-level parallelism techniques
Optimize memory, compute, and data flow to meet real-time or high-throughput constraints
Improve the performance, reliability, and observability of our inference backend across diverse compute targets (CPU/GPU)
Collaborate with cross-functional teams (including researchers, developers, and designers) to deliver efficient and scalable inference solutions
Contribute to ComfyUI and internal infrastructure to improve the usability and performance of model execution flows
Investigate performance bottlenecks at all levels of the stack-from Python to kernel-level execution
Navigate and enhance a large, complex, production-grade codebase
Drive innovation in low-level system design to support future ML workloads
Requirements:
5+ years of experience in high-performance software engineering
Advanced proficiency in CUDA, C/C++, and Python, especially in production environments
Deep understanding of GPU architecture, memory hierarchies, and optimization techniques
Proven track record of optimizing compute-intensive systems
Strong system architecture fundamentals, especially around performance, concurrency, and parallelism
Ability to independently lead deep technical investigations and deliver clean, maintainable solutions
Collaborative and team-oriented mindset, with experience working across functional teams
This position is open to all candidates.
 
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עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
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