דרושים » חומרה » Senior Core Power Management Architect

Requirements:
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
At least 20 years of experience in one of the leading CPU companies
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
QUALIFICATIONS
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Minimum of 10 years of proven design experience in complex processor projects.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to US, Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills
MINIMAL REQUIREMENTS
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
Ownership of the overall verification methodology for a CPU project.

Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Solid understanding of general purpose CPU micro-architecture, including load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory technologies and memory controllers.
Ability to make trade-offs between power, performance and area to meet the requirements of the product.
Hand-on experience with high power-efficient CPU on chip interconnect, coherent fabric, memory controllers.
At least 8 years experience in architecture in one of the leading CPU companies
Experience modeling microprocessors using higher-level languages, like C/C++.
DESIRED
Co-operate and communicate well with the architecture and design teams.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Good understanding of CPU design methodology
Excellent verbal and written communication skills.
CPU related Experience in one of the leading CPU companies or in academia.
Willing to relocate to China for extended period.
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Experience modeling microprocessors using higher-level languages, like C/C++.

Requirements:
BS or MS Degree in Electrical Engineering
At least 10+ years of significant board design and systems and working with multi-disciplinary products and High-speed design.
Experience in architecture definition - Clocks, Resets, Interconnects, DDR Memory Controller, Boot, Power Management, Thermal, System Performance, IO technologies, (PCIe, ETH, USB, etc), CPU and Platform integration.
Experience in solving issues at all levels of architecture definition.
Demonstrated experience working on sophisticated automotive systems. Architecture/development experience - advantage
Deep understanding of MIPI and SerDes (like as FPD-Link, GMSL and A-PHY), Functional Safety, ISO26262 standards - advantage

Requirements:
Skill Requirements:
Experience in HW modeling using systemC, including all stages of backend flow: synthesis and power measurements. Experience with working in a team with various discipline. Having good communication skills. Hands on and self contained.

Requirements:
B.Sc. or M.Sc. in Electrical or Computer Engineering (or related field).
5+ years experience in SOC architectural roles
Technical knowledge: Strong understanding of SoC design flows, and system requirements.
Power and performance analysis: Ability to analyze and balance performance, power, and area trade-offs.
Strong system thinking - ability to move between micro-architecture depth and system-level abstraction.
Hardware and software collaboration: Proven experience working across hardware and software teams to achieve system goals.
Experience defining and documenting architecture specifications, interfaces, and integration flows.
Excellent communication and collaboration skills, with the ability to lead cross-functional discussions and influence stakeholders.
Experience as a Functional Safety manager, advantage
Proactive, curious, and detail-oriented - capable of balancing innovation and practicality.

Requirements:
BSc / MSc / PhD in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in VLSI / ASIC design, chip architecture, or micro-architecture of complex blocks.
Proven experience leading or managing a small team of designers, verification engineers, or HW architects.
Ability to take an idea into implementation.
Strong background in high-speed networking systems, such as:
o Ethernet Switches
o NPUs
o NICs
o Traffic Managers
o Fabric Switches
o High-performance processors
Skills
What Were Looking For
Strong technical leadership with the ability to drive architectural vision.
Excellent written and verbal communication skills in English.
Outstanding collaboration and teamwork skills across disciplines and organizational levels.
Independent, self-driven, and comfortable taking full ownership of complex challenges.
Passion for innovation and cutting-edge networking technologies.
Highly motivated with a proactive, can-do mindset.

Requirements:
BSc / MSc / PhD in Electrical Engineering, Computer Engineering, or a related field.
7+ years of experience in VLSI / ASIC design, chip architecture, or micro-architecture of complex blocks.
Strong background in high-speed networking systems such as:
o Ethernet Switches
o NPUs
o NICs
o Traffic Managers
o Fabric Switches
o High-performance processors
Skills
What Were Looking For
Excellent written and verbal communication skills in English.
Strong collaboration skills and the ability to work effectively across teams and disciplines.
Independent, self-driven, and capable of deep technical ownership.
Passion for innovation and cutting-edge technology.
Highly motivated with a proactive mindset.

Requirements:
Four or more years of experience in one or more of the following roles in the memory cluster of an Out of Order CPUs:
Architecture or micro-architecture definition.
Performance modeling and studies.
RTL implementation.
Verification of Multithreading.
Education: Academic degree in Computer Engineering or Computer Science
Advantages:
Knowledge and experience in memory ordering architecture.
HW or SW Experience in inter-thread synchronization.
Knowledge of the arm Instruction Set Architecture.
Skills
Good verbal English skills.
Good interpersonal skills
Team player.