דרושים » הנדסה » Senior Physical Design Backend Engineer

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לפני 3 שעות
Location: Yokne`am and Tel Aviv-Yafo
Job Type: Full Time
we ae looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Own the special chiplet STA, analyze the timing results, verify correctness and provide budget for the different partitions.
Generate the timing constraints for the STA and the P&R flow.
Be exposed and work on a variety of exciting designs (including high cell count and high frequency), resolving complex timing and congestion problems.
Help to shape clock tree, and effect the work of the different teams (Front end, DFT & BE).
Daily work involves all aspect of STA & chip design: take part in SDC generation & review, actively running & analyzing STA tools, guiding the group during chip closure process, etc'.
Taking part inflows development.
Take part in ramping up new breaking technologies.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience
5+ years of hands-on STA experience.
Experience in Prime Time and signoff methodologies.
Deep understanding of all aspects of Physical construction and Integration.
Great teammate.
This position is open to all candidates.
 
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13/11/2025
Location: Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part in flows development.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.

5+ years of experience in Physical Design.

Proven experience in RTL2GDS flows and methodologies.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Deep understanding of all aspects of Physical construction and Integration.

Strong background of Physical Design Verification methodology LVS/DRC.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc).

Great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 2 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part in flows development.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.
5+ years of experience in Physical Design.
Proven experience in RTL2GDS flows and methodologies.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Deep understanding of all aspects of Physical construction and Integration.
Strong background of Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc).
Great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
23/11/2025
חברה חסויה
Location: More than one
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of exciting designs. Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part in flow development.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Deep understanding of all aspects of Physical construction and Integration.

Knowledge in Physical Design Verification methodology LVS/DRC.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

2-3 years of relevant experience.

Great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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18/11/2025
חברה חסויה
Location: More than one
Job Type: Full Time
We are looking for best-in-class STA Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.


What you will be doing:

STA analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.

Taking part inflows development.
Requirements:
What we need to see:

B.SC. in Electrical Engineering/Computer Engineering.

2-5 years of experience as STA engineer.

Ability to quickly adapt to new technology and go deep into new areas.

Strong communication skills.

Great teammate.

Drive new solutions based on any issues that arise.


Ways to Stand Out From the Crowd:

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני דקה
חברה חסויה
Location: More than one
Job Type: Full Time
we are looking for best-in-class STA Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
STA analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part inflows development.
Requirements:
B.SC. in Electrical Engineering/Computer Engineering.
2-3 years of experience as STA engineer.
Ability to quickly adapt to new technology and go deep into new areas
Strong communication skills
Great teammate.
Drive new solutions based on any issues that arise
Ways to Stand Out From the Crowd:
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
19/11/2025
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.

Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.

Power estimation and power modeling.
Requirements:
B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.

2+ years of experience in physical design and/or BE power optimization aspects.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage.

FE design experience is an advantage.

Excellent problem-solving, partnership, and interpersonal skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
16/11/2025
חברה חסויה
Location: Yokne`am
Job Type: Full Time
We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilites:
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.
Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
8+ years experience in full chip design.
Experience in leading the full-chip level design and successfully taping out multiple intricate SoCs.
Experience in floor planning, integration, signoff methodologies, and signoff tools for hierarchical designs.
Experience with SoC design practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
Expert knowledge of the entire backend design flow from RTL to TO.
Experience with STA (Static Timing Analysis) tools like primetime or tempus.
Experience with IR drop tools like Ansys Redhawk or Volta's.
Physical Verification Expert (DRC/LVS).
Strong independent and motivated to learn quickly, hard-working, and is results oriented.
Good social skills and ability to work collaboratively with other teams.
Preferred:
Experience with high-speed serial interfaces such as PCIe, DDR, Ethernet.
Familiarity with advanced DFT flows & tools.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
16/11/2025
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Senior Chip Design Verification Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency!

Come and take a significant part in designing and verifying our groundbreaking and innovating new chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you'll be doing:

Take a crucial part in developing our next-generation chip controller

Design and verification with challenging multi-discipline context

Take part in the development of all our networking and GPU networking chips and systems.
Requirements:
What we need to see:

B.SC./ M.SC. in Computer Engineering/Electrical Engineering/Communication Engineering.

5+ years of validated experience in ASIC Verification.

High Level of English.

Good teammate.

Ways to stand out from the crowd:

Background in Specman.

Knowledge in HDL (Verilog/VHDL).

Knowledge in Mixed Signals, Analog, and Behavioral Models for Verification.

Knowledge in Chip boot and Infrastructures.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
19/11/2025
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Chip Design Verification and Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating new chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you'll be doing:

Take a crucial part in developing our next-generation chip controller.

Design and verification with challenging multi-discipline context.

Take part in the development of all our networking and GPU networking chips and systems.
Requirements:
What we need to see:

B.SC./ M.SC. in Computer Engineering/Electrical Engineering/Communication Engineering with high scores, or equivalent experience.

2+ years of validated experience in ASIC Verification and/or RTL (Chip Design).

High Level of English.

A team player with good communication and interpersonal skills.

​Ways to stand out from the crowd:

Background in Specman.

Knowledge in HDL (Verilog/VHDL).

Experience in Mixed Signals, Analog, and Behavioral Models for Verification.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 2 שעות
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
we are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What youll be doing:
Work in a combined design and verification team that develops front-end design for the Switch silicon GPU and HCA.
Chip level integrations and connectivity.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. Interaction with organization-wide groups.
Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate, or equivalent experience.
2+ years of experience in RTL verification
Self-motivated, ability to work independently and drive tasks to completion
A team player with good communication and interpersonal skills.
Ways to stand out from the crowd:
Knowledge in Specman, Verilog
Background in Networking.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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