דרושים » תוכנה » מהנדסת או מהנדס תקשוב במערך מחשוב ומערכות מידע JB-2293

In this role you will be responsible to model, analysis and estimate power consumption of daily use cases on our next generation SoCs. Drive new ideas into micro-architecture, design and circuits to reduce SoC power across the dynamic range. Drive budgeting, measurement and analysis of overall SoC power for many use cases of interest. You Will work extensively with many teams across every stage of the project from Architectural definition through Design implementation and SW management to focus on power optimization.
To be successful in this role, you must have keen interest and motivativation to deliver best experience to our users, and wide perspective in order to work simultaneously on multiple disciplines. This role is required working closely with many cross-functional teams and good understanding of hardware and software interaction at system level.

In this highly visible role, you will be responsible for SOC power simulation and power modeling, SOC use case power analysis, and drive the future SOC power optimization.

As a PNR/PD-CAD team member, you will have an impact on a wide range of activities and domains in the PD world. The team develops and supports utilities that enable an efficient work environment for the physical design teams across the world.

The role includes exploring new technologies and methodologies of first-of-its-kind designs, and the complex implementation of designs from small ones to the largest possible.
The job includes hands-on work and impact on all aspects of the design cycle, from infrastructure-related automation for design efficiency through developing internal PNR flows, which will enable improved designs - from PNR implementation through developing infra, signoff flows & verification utilities.

Responsibilities:
The job includes constant work with different teams and disciplines that interface with the PNR world, which includes Timing, power delivery, synthesis, Physical Verification, and more.
Along with the different disciplines, you will work with different teams, from vendors, PD team members and other CAD team members and discipline owners across the world to enable and improve the productivity of the PD flows.

In your role as a senior PHY Algorithms Development Engineer, as part of Apple Connectivity Group, you will be part of a world-class group that pioneers design and development of Physical Layer algorithms for wireless communication systems for Apple products. We live in a mobile and device driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. Apple is meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that commitment. The success we are targeting will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problem in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk.

We are looking for a candidate who can innovate and integrate signal processing technologies for solving novel and diverse sets of problems in various wireless communication and sensing technologies:
- Develop communication signal processing algorithms for best-in-class implementation of various wireless standards.
- Conduct basic research of existing solutions in literature.
- Involvement in block level spec definition.
- Perform mathematical analyses of the given problem and its proposed solutions.
- Implement floating-point simulations to prove spec compliance of suggested solutions.
- Implement fixed-point modeling and simulation to allow performance sign-off and RTL bit-exact development.
- Write detailed design documents that will enable implementation of algorithms by other teams specializing in either RTL design or DSP firmware coding.
- Optimize and fine-tune the system for spec compliance on silicon in an RF lab environment.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

We are a multidisciplinary development team working on a cutting-edge autonomous driving project, at the forefront of automotive technology. The team develops complex ECUs that combine multiple SoCs, low-level firmware, hardware, validation, and automation systems, enabling next-generation autonomous capabilities. We work closely with hardware, system, verification, and automation groups to bring up, debug, and validate advanced automotive platforms from early development stages through production. This is a highly technical, hands-on environment focused on solving real system-level challenges.
What will your job look like:
Debug complex HW/FW and system-level issues in an autonomous vehicle platform
Perform deep root-cause analysis across firmware, hardware, and automation systems
Lead firmware bring-up, integration, and debug of ECUs with multiple SoCs
Debug and support automation systems, including lab automation and FW verification environments
Analyze failures originating from automated test systems and distinguish between FW, HW, and test infrastructure issues
Work closely with HW, system, validation, automation, and architecture teams
Support issues from early development stages through production and field failures
Contribute to firmware debug methodologies and verification strategies
Provide technical leadership and mentoring when needed