דרושים » הנדסה » Emulation & Prototyping Engineer

we are looking for a best-in-class Chip Design HW Emulation Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in emulating our groundbreaking and innovative chips, enjoy working in a meaningful, growing, and highly professional environment where you make a huge impact in a technology-focused company. Join our company's world-class emulation team in Israel. Our focused team takes Switches/NICs/SoCs designs and program the emulators to behave like our silicon. Are you ready to take on interesting problems and craft solutions? Come check out our team.
What you will be doing:
Responsible for emulation and prototyping of complex chip designs.
Define methodologies and develop infrastructure to enable fast integration of large chips into hardware emulation platforms.
Collaborate closely with design, verification, and software teams to support embedded and application software development.
Connect emulator/FPGA-based solutions to real external hardware or virtual targets.
Manage complex testbenches and support various hardware/software protocols.
Perform RTL design, verification, FPGA partitioning and implementation.
Develop scripts to automate flows and improve efficiency.
Bring up and debug designs in the lab environment.
Work in a cross-functional, hands-on engineering role that spans hardware and software domains.

We are looking for an excellent Senior Firmware Verification Engineer to join the Firmware team. The company Firmware team develops groundbreaking networking features for AI, cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With many hardworking engineers around the globe, the work environment is complex, results-oriented and fast paced. You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed
What you will be doing:
Work closely with the architecture and different software and hardware design teams.
Implement new features for our company NIC and Switch firmware.
Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.
Collaborate with multi-functional teams including chip design, board designers, Silicon, SW and program managers to debug any FW/validation issues.
Heavily involved with the early modeling and simulation required to produce our outstanding products including schematic and layout reviews on next generation board designs.

We are looking for a Senior Chip Design Verification Engineer for developing the next generation DFT technologies.
As a Senior Chip Design Verification Engineer in the DFT team at our company, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
What you'll be doing:
In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.
As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.
Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

We are looking for a Senior Chip Design Verification Engineer for developing the next generation DFT technologies.
As a Senior Chip Design Verification Engineer in the DFT team at our company, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
What you'll be doing:
In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.
As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.
Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks
Taking part in flows development and deployment.

We are looking for Physical Design Engineer.

Roles and responsibilities:
Build, maintain, and optimize CAD tools infrastructure supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
Develop and automate IC layout flows, including placement, routing, floorplanning, PCells, and tapeout preparation.
Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
Design and implement testing frameworks, regression suites, code review practices and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.

We are looking for a Chip Design Verification Manager for developing the next generation DFT technologies.
As a Chip Design Verification Manager in the DFT team at our company, you will lead teams that verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
What you'll be doing:
In this position you will be responsible to lead verification teams in the the definition, flow and execution of verification of the DFT design, architecture and micro-architecture.
As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.
Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.

Roles and responsibilities:
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

we are an industry leader with groundbreaking developments in High-Performance Computing & Networking, Artificial Intelligence, and Visualization. Our work opens up new universes to explore, enables outstanding creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to self-driving cars!
We are now looking for an outstanding, creative & hardworking Firmware PHY/Algorithms Engineer to join our team. You will be responsible for firmware development, characterization & validation of state-of-the-art network devices. Work as part of a team with circuit design, algorithm, architects & HW design to ensure outstanding product development from concept to customer satisfaction. The qualified candidate should be comfortable working on different code environments and should demonstrate a passion for the creation, execution, and improvement of FW features to control mixed-signal circuits.
What youll be doing:
Implement FW functionality in signal processing units of our company products
Work closely with the architecture, HW, and SW design teams
Define implement and maintain FW algorithm to control the Silicon
Develop and test FW on emulation & simulation environments during the Pre-silicon phase
Debug and screen HW/FW/SW issues
Take an active part in silicon bring-up and SW development phases
Lead data-driven discussions about the product functionality and areas for improvement.

We are looking for a creative and independent Test Engineer with hands-on experience in digital test content development (ATPG, LBIST, MBIST).Our high-speed networking products are industry leaders, continually redefining speed, bandwidth, and reliability across generations.
In this role, you will be responsible for developing, validating, and supporting digital test content for our companys advanced Network Silicon ICs (Switches, NICs, SmartNICs). You will work closely with DFT, design, and test engineering teams to ensure high-quality and scalable test content from wafer to final product.
What you'll be doing:
Develop ATPG, LBIST, and MBIST content based on DFT architecture
Run validation flows (simulation/emulation/silicon), analyze failures, and debug pattern issues
Collaborate with DFT teams to ensure alignment between test logic and content implementation
Support test program bring-up and pattern integration on production testers
Continuously improve coverage, pattern quality, and pattern generation efficiency
Work with product and test engineering to support yield improvement and debug activities.