Chip Design Hardware Emulation Engineer

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8333493

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3 ימים

Physical Design Signoff CAD Engineer

חברה חסויה

Location: Yokne`am

Job Type: Full Time

we are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.
Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence.
Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.
Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).
1+ years of experience
Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.
Ownership, self-learning skills, and ability to work autonomously
Ways to stand out from the crowd:
Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality)
Knowledge in Tcl/Perl/Python
Versatile
Great teammate.

This position is open to all candidates.

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8329733

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4 ימים

Senior VLSI Integration Engineer

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

we are looking for best-in-class Senior VLSI integration Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Implement Chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design) .
Be exposed and work on a variety of functional and structural challenges. Including functional debug, getting ready for physical design, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks
Taking part in flows development and deployment.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
10+ years of actual design experience in chip design
Solid hands-on RTL design skills in System-Verilog
Passion for quality and readiness to physical design, emulation, firmware and other customers
Proficiency in at least one scripting languages like python, bash, tcl.
Great teammate.

This position is open to all candidates.

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8328305

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25/08/2025

Senior Chip Design Engineer, Port IP Group

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

we are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you'll be doing:
Join the Tel Aviv group, working on designing the new generation of high-speed ports.
Design for chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area, and performance
Daily work might involve any or all aspects of chip development: Verification, Design, and Micro-Architecture.
Work closely with Firmware and other groups around the globe.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Communication Engineering/Computer Engineering
5+ years of validated experience in RTL Frontend ASIC Design or Verification (Chip Design).
Strong debugging, problem-solving and analytical skills.
A great teammate with strong communication and interpersonal skills.
Ways to stand out from the crowd:
Knowledge in Specman.
Knowledge in Verilog.

This position is open to all candidates.

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8318162

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4 ימים

Senior CDC Engineer, Chip Design

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. We make outstanding artificial intelligence happen and accelerate Open-AIs Chat-GPT, for example. We believe in our people and products and seek excellent people to join us!
We are looking for a CDC Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
You will play a major role analyzing the design and driving fixes as well as developing, maintaining, and improving our Lint, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) constraints and methodology for our SOCs across block level, cluster level, and/or full chip level.
Responsibility for analyzing and optimizing the CDC and RDC sign-offs.
Develop and maintain key CDC/RDC checks and associated sign-offs for SOCs.
Help in driving frontend and backend assertions needed to support CDC/RDC constraints and assumptions.
Learn and understand the switch u/architecture to support the design and verification teams.

Requirements:
B.Sc. in Electrical Engineering from a known university.
Excellent grades.
5+ years of experience in ASIC design/uarch/arch/performance.
At least 4 years of hands on experience in writing Verilog/VHDL.
Strong analytic capabilities, and passion for solving logical issues.
Strong debug skills.
Experience in Python, Tcl and Make for automation and scripting tasks.
Ability to drive complex activities involving many interfaces and teams.
Good communication skills.
Ways to stand out from the crowd:
Experience in RTL Design, Synthesis and Timing and as an HW-architect.
Experience with tools like Synopsys PrimeTime, Spyglass, VC-Static, or Meridian.
Knowledge in switching fabrics with strict performance requirements. (Networking, SOC connectivity, etc).
Familiar with working on large high-end ASICs.
Experience in performance improvements in ASICExpertise in Static Timing Analysis (STA), Clock-Domain Crossing (CDC), and Reset Domain Crossing (RDC) solutions.

This position is open to all candidates.

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8327880

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4 ימים

Physical Design Backend Engineer

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

we are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.
2+ years of experience in physical design.
Proven experience in RTL2GDS flows and methodologies.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate.

This position is open to all candidates.

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8328348

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26/08/2025

Physical Design Manager

חברה חסויה

Location: Be'er Sheva and Tel Aviv-Yafo

Job Type: Full Time

we are looking for best-in-class Physical Design Manager to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Manage and Lead Physical Design team, up to 10 engineers.
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.
5+ years of physical design team management.
5+ years of experience in physical design overall.
Proven experience in RTL2GDS flows and methodologies.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate.

This position is open to all candidates.

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8319701

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25/08/2025

STA Backend Engineer

חברה חסויה

Location: More than one

Be'er Sheva

Tel Aviv-Yafo

Yokne`am

Job Type: Full Time

we are looking for best-in-class STA Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
STA analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part inflows development.

Requirements:
B.SC. in Electrical Engineering/Computer Engineering.
2-3 years of experience as STA engineer.
Ability to quickly adapt to new technology and go deep into new areas
Strong communication skills
Great teammate.
Drive new solutions based on any issues that arise
Ways to Stand Out From the Crowd:
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

This position is open to all candidates.

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8317724

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25/08/2025

Physical Design Team Manager

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

we are looking for best-in-class Physical Design Team lead to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
Leading and mentoring Physical Design-Backend team.
Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.
Take part in project definition towards POR, close interaction with other domains such as FE, ARCH.

Requirements:
B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
2+ years of managerial experience.
6+ overall years of experience in physical design.
Proven experience in RTL2GDS flows and methodologies.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate.

This position is open to all candidates.

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8317777

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28/08/2025

Senior Physical Design Backend Engineer

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

we are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part in flows development.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.
5+ years of experience in Physical Design.
Proven experience in RTL2GDS flows and methodologies.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Deep understanding of all aspects of Physical construction and Integration.
Strong background of Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc).
Great teammate.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8322820

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