דרושים » חשמל ואלקטרוניקה » Embedded Software Engineer

Join our group and take a major part in redefining the future of AWS cloud. Were searching for engineers with a passion for networking to develop SRD (Scalable Reliable Datagram). SRD is a high-performance, low-latency transport protocol used within our infrastructure to optimize network performance. SRD powers several high-impact, cutting-edge products, including on-demand ML and HPC platforms leveraging EFA, next-generation storage services built on EBS, and the future of AWS network traffic.

As an Embedded Software Engineer on the SRD team, your primary responsibility will be to develop and optimize SRD technology across AWSs network infrastructure. You will work on cutting-edge, high-performance platforms that power ML, HPC, and storage-intensive workloads.
Your role will involve designing, deploying, and maintaining the SRD codebase, ensuring its reliability and scalability to meet the demands of diverse applications. You will gain in-depth knowledge of the various platforms and services running SRD within AWS, diving deep to understand their unique challenges and complexities.

Collaboration will be key, as you will work across multiple teams at different layers of the software stack. You will also contribute to defining new hardware modules and enabling offloads to enhance performance.

Key job responsibilities:
As an Embedded Software Engineer in the SRD team your primary role will be to develop and optimize the implementation of SRD technology across AWS's network infrastructure. Your responsibilities will encompass designing, deploying, and maintaining SRD code-base, ensuring its reliability and scalability to accommodate the demands of various applications.
Youll be familiar with the different platforms and services that run SRD in AWS. Youll need to deep-dive to understand the different challenges and complexities each of them has. Youll work with multiple teams both on layers bellow and above SRD SW stack often even define new Hardware modules and enable new offloads to optimize performance.

We are looking for an Embedded Software Engineer to join the SW group and take a major part in redefining the future of our cloud.
Were searching for engineers with a passion for networking to develop SRD (Scalable Reliable Datagram). SRD is a high-performance, low-latency transport protocol used within our Web Services infrastructure to optimize network performance. SRD powers several high-impact products, including on-demand ML and HPC platforms leveraging EFA, next-generation storage services built on EBS, and the future of our network traffic.

As a Senior Network Software Engineer on SRD team, your primary role will be to develop and optimize the implementation of SRD technology across our network infrastructure. Your responsibilities will encompass designing, deploying, and maintaining SRD code-base, ensuring its reliability and scalability to accommodate the demands of various applications. An essential part of your role will involve conducting extensive network simulations to evaluate system performance under different conditions, enabling you to identify potential bottlenecks and inefficiencies. Using these simulations, you will troubleshoot network issues and implement robust solutions, leading to minimal data loss and latency. Leveraging your in-depth understanding of network protocols and our infrastructure, you'll refine and improve the SRD system's performance. Furthermore, you will be expected to mentor junior team members, leading projects to advance the SRD capabilities within the environment. Staying updated with the latest industry trends and incorporating them into strategic network service planning.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
You will be responsible for performance analysis for an end-to-end networking stack using your deep knowledge of RDMA based transports.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Participate in evaluation of future ASIC designs and general architecture for executing our companys data center networking roadmap: off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will be responsible for performance analysis for an end to end networking stack using your deep knowledge of RDMA based transports.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Participate in evaluation of future ASIC designs and general architecture for executing our companys data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how everything interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro-architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will help to develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our Application-specific integrated circuit (ASIC) projects. You will provide emulation infrastructure and methodologies for supporting these projects. You will work with other emulation team members as well as designers, verification engineers, and software teams. You will work with with our external vendors, lab support teams, networking and security, and Electronic Design Automation (EDA) tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects. You will also assist in compiling projects specifying our prototyping platforms, debugging issues in both infrastructure and design, assisting in the hardware and lab bring up, and verification of our ASIC systems.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Help in maintaining and upgrading emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in our company infrastructure.
Support emulation team members with debugging hardware, tooling, and project specific issues.
Help to bring up external interfaces (e.g., USB, PCIe, Ethernet, etc.) on the emulation platforms, and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

Required Distributed Computing Software Engineer
Hod Hasharon \ Haifa
Job Description:
Our team at the Huawei Computing Network Innovation Lab is looking for exceptional talent to join us and lead the development of next generation data centers. We create cutting-edge technologies that synergize software and hardware in tandem to accelerate compute, storage and networking at large-scale. We aim to drive innovations and deliver software defined infrastructure and algorithms to HPC and AI/ML in distributed run environment.
We are looking for outstanding candidates with hands-on experience in software development. If you are a team player with excellent communication skills and motivation to investigate state-of-the-art directions and revolutionize application performance, youre welcome on board!
What will you be doing?
Envision, design and develop new features in all layers of the HPC / AI stack, from the application level, through the programming model (e.g. OpenMP, MPI) and down to the supporting libraries/middleware
Research, design and implement features for HPC / AI applications using parallel programming models (e.g. OpenMP, MPI), accelerators offloading and memory tiers.
Contribute to open-source scientific computing, networking and I/O libraries
Research, design and assist in developing hardware offloads for features relevant for scientific, deep learning, and data-intensive workloads.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical problems with micro-architecture and solutions, and evaluate design options with performance, power, and area.The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

The Graviton Software team is looking for Software Engineers to develop tools to drive the optimization of open source and internal applications. part of us, designed Graviton as a strategic initiative to improve how software works at our scale. Graviton is Arm-based CPU that delivers better performance, lower price and lower carbon footprint over comparable x86-based instances.

Key job responsibilities
As a Software Developer, you will:
- Build software framework for tools to analyze performance of hardware and software components.
- Leverage existing perf tools like sysstat, sysctl, perf, etc.
- Automate the collection and analysis of processor, OS and workload performance data.
- Help external customers and various internal services like Lambda, Elastic Map Reduce, ElastiCache, and RDS to troubleshoot bottlenecks and to optimize the architecture, algorithms, and deployment on Graviton.
- Work on Linux and other open source code, improving it and contributing the changes back to the community.
- Play an instrumental role in driving the roadmap to deliver cost-effective and performant computing systems.
- Use and further develop your deep knowledge in areas including design, implementation, and data analysis.
- Have the opportunity to lead the innovation and deliver software that powers the world largest cloud provider.
- If you are already an open source developer or passionate about it, you will be able to continue your passion and contribute back to the community across all those projects.

About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and verification closure. You will verify digital designs and collaborate with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
The ML, Systems & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.