דרושים » תוכנה » VLSI Verification Team Lead

Requirements:
BSc in Electronics Engineering.

10+ Years of industry experience in Design.

Team Player, with excellent interpersonal skills.

Highly Motivated.

Acquaintance with all aspects of chip development.

Micro-Architecture.

Design and verification tools and methodologies.

Experience with Verilog RTL coding and Verification support.

Experience and synthesis flows an advantage.

Working with FW and SW engineers.

Requirements:
BASIC QUALIFICATIONS:
- Electrical/Computer Science engineer.
- 8+ years of experience with full-chip/system-level verification of a large-scale SoC.
- Experience with SW development (C/C++/Assembly).
- Sound understanding and knowledge of object-oriented programming concepts.
- Hands-on experience with emulation/silicon debugging, waveform debugging, and code coverage analysis.

PREFERRED QUALIFICATIONS:
- Knowledge of ARM architecture.
- Knowledge of the following programming languages: Perl/Bash/TCl/Python.
- Knowledge of PCIe, Processors, Ethernet, DDR.
- Knowledge of Hardware Verification concepts and tools (UVM , Coverage Driven verification).
- Verilog/SystemVerilog/Specman.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
5 years of experience in technical leadership, leading project teams, or setting technical direction.
Experience in managing Design Verification (DV) team.
Experience in verification methodologies, tools, and techniques.
Experience creating chip or subsystem design verification strategies and plans.

Preferred qualifications:
Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
Experience with verification techniques, and full verification life cycle.
Experience in verification of IP/SoC/ASIC.
Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
Experience with ARM instruction set architecture or processor microarchitecture.
Experience in leading teams and delivering projects.

Requirements:
BSc in electrical engineering, computer engineering, or computer science
8+ years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++)
System Verilog writing skills, preferably in OVM/UVM
SW embedded experience, C/C++ skills
TestPlan defining and Coverage-Driven Verification experience
3rd-party IPs integration testing experience
Waveform debugging with the latest EDA tools, root-cause bugs independently
Skills in scripting Perl/Python - Advantage
Knowledge in Industry Standard protocols such as AXI/OCP/APB - Advantage.

Requirements:
7+ years of experience as a Verification Engineer.

B.Sc./M.Sc. degree in electrical/computer engineering from a leading university.

Experience in pre-silicon functional unit level/fullchip verification.

Experience in leading block/cluster verification from scratch.

Experience in System Verilog UVM.

Experience in verification of complex SoC and designs.

Experience with AMBA protocols and NOC subsystem is an advantage.

Experience with CPU subsystem is an advantage.

Experience with PCIe is an advantage

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.

Preferred qualifications:
Masters degree in Electrical Engineering or Computer Science.
Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
Experience with CPU implementation, assembly language, or compute SOCs.

Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.

Preferred qualifications:
Masters degree in Electrical Engineering or Computer Science.
Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
Experience with CPU implementation, assembly language, or compute SOCs.

Requirements:
BSc in electrical engineering, computer engineering or computer science
5+ years of experience working in verification environment, tests, and test bench development (C/C++/SV)
TestPlan defining and Coverage-Driven Verification experience
Fullchip/SOC verification experience, strong system understanding
3rd-party IPs integration testing experience
Waveform debugging with the latest EDA tools, root-cause bugs independently
Knowledge in Industry Standard protocols such as AXI/OCP/APB
SW embedded experience, C/C++ skills - Advantage
Strong skills in scripting Perl/Python - Advantage
System Verilog writing skills, preferably in OVM/UVM Advantage.

Requirements:
You hold a Bachelors degree in Electrical Engineering, Computer Engineering, or a related field, with a Masters degree being a plus.
You have 10 years of hands-on experience in design and verification of ASIC/FPGA and mixed signal systems, particularly in the realm of image sensors or closely related technologies.
You have at least 5-7 years of experience in a leadership or managerial role.
You possess a solid background in ASIC/FPGA development, including experience with HDL coding, verification methodologies such as UVM, backend and system interfaces.
You are proficient with common industry digital design tools and simulation software, such as Cadence/Synopsys, and FPGA environments Xilinx/Intel.
Your excellent leadership, communication, and project management skills empower you to thrive in a fast-paced, collaborative environment.
You are adept at managing multiple projects simultaneously, ensuring timely and high-quality deliverables.
An advantage - expertise in embedded systems and firmware development, as well as knowledge of Backend flow, manufacturing processes, and design for test (DFT) methodologies.

Requirements:
BSc in electrical engineering, computer engineering, or computer science
Passion for the field of Formal Verification
3+ years of experience in Formal Verification
Understanding and mastering hardware description languages (HDLs) like Verilog/SystemVerilog and programming languages such as Python or C++
Strong analytical and problem solving skills
Ability to work independently and in a team-oriented environment
Participating in last semester Formal Verification course in the Technion - advantage.