דרושים » מדעים מדוייקים » Experienced SoC Verification Engineer

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Location: Petah Tikva
Job Type: Full Time
Which team will you join?
our company EyeC VLSI team - a group designing the chips for Radar systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
You will take a central hands-on role in Design Verification.
Define Environment micro-Architect, Implement complex UVM environment, Build vPlan .
Execute coverage implementation.
Be part of external IP verification and Internal custom IP.
Be part of System definition and top-level activity.
Take part in Silicon bring-up.
Requirements:
Bsc/MSC in Electrical engineering/Computer engineering .
Over 5 years of experience in a design verification role .
Experience in UVM.
Experience in System Verilog.
Experience in high-speed I/F - Advantage.
This position is open to all candidates.
 
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חברה חסויה
Location: Petah Tikva
Job Type: Full Time
Which team will you join?
our EyeC VLSI team - a group designing the chips for Radar systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.

What will your job look like:
You will take a central hands-on role in Design Verification.
Define Environment micro-Architect, Implement complex UVM environment, Build vPlan .
Execute coverage implementation.
Be part of external IP verification and Internal custom IP.
Be part of System definition and top-level activity.
Take part in Silicon bring-up.
Requirements:
Bsc/MSC in Electrical engineering/Computer engineering .
Over 7 years of experience in a design verification role .
Experience in UVM.
Experience in System Verilog.
Experience in high-speed I/F - Advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8169114
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Petah Tikva
Job Type: Full Time
The company's EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.
Requirements:
BSc in Electrical engineering/Computer Engineering.
Over 5 years of experience in Logic design.
Experienced in all ASIC flow from definition to implementation.
Experience in design for power- Advantage.
Experience in High-speed I/Fs or algorithm blocks - Advantage.
Knowledge in CDC and low power flow - Advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8170505
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מה השם שלך?
תיאור
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סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Petah Tikva
Job Type: Full Time
The company's EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.
Requirements:
BSc in Electrical engineering/Computer Engineering.
Over 7 years of experience in Logic design.
Experienced in all ASIC flow from definition to implementation.
Experience in design for power- Advantage.
Experience in High-speed I/Fs or algorithm blocks - Advantage.
Knowledge in CDC and low power flow - Advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8169100
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מה השם שלך?
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שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Petah Tikva
Job Type: Full Time
our company, a world leader in driver assistant systems and autonomous vehicles, is looking for SW Embedded Engineer engineer for the range of its next generation SoCs supporting its radar systems
Our team is responsible for validating our company's radar SoCs, utilizing Pre-Silicon environments, as well as Post-Silicon platforms.
We are developing fully embedded C++ based validation environment for our needs.
You will be taking part in developing anything from environment and drivers through system modules such as file system, network stack, memory management and more, and up to complex automation tools in both C++ and python.
What will your job look like
Get a deep understanding of our chip hardware IP blocks, both analog and digital.
Develop our validation environment.
Develop, port, or add features to the product drivers using Technical Specs and existing modules.
Define, develop and execute various complex validation scenarios on the SoC.
Debug complex SoC problems using embedded GDB, JTAG probes, going down to signal level using scopes.
Take part in Next Gen SoC's Power-On's and platforms Bring-Up's.
Collaborate with other SW/Embedded and HW/Electrical Validation teams across the company.
Requirements:
BScin electrical engineering, computer engineering or computer science.
5+ years development experience in embedded C++.
3+ years System Validation experience.
Ability to read complex HW specifications and define a series of tests based on them.
Experience working in multi-core environments.
Experience working with real-time OS and bare metal device drivers.
Developing experience in python - advantage.
Experience with Embedded systems and driver development - advantage.
A "Can Do" attitude .
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8169107
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Petah Tikva
Job Type: Full Time
our company, a world leader in driver assistant systems and autonomous vehicles, is looking for talented silicon validation engineer for the range of its next generation SoCs supporting its radar systems
Our team is responsible for validating our company's radar SoCs, utilizing Pre-Silicon environments, as well as Post-Silicon platforms.
We are developing fully embedded C++ based validation environment for our needs.
You will be taking part in developing anything from environment and drivers through system modules such as file system, network stack, memory management and more, and up to complex automation tools in both C++ and python.
What will your job look like
Get a deep understanding of our chip hardware IP blocks, both analog and digital.
Develop our validation environment.
Develop, port, or add features to the product drivers using Technical Specs and existing modules.
Define, develop and execute various complex validation scenarios on the SoC.
Debug complex SoC problems using embedded GDB, JTAG probes, going down to signal level using scopes.
Take part in Next Gen SoC's Power-On's and platforms Bring-Up's.
Collaborate with other SW/Embedded and HW/Electrical Validation teams across the company.
Requirements:
BScin electrical engineering, computer engineering or computer science.
5+ years development experience in embedded C++.
3+ years System Validation experience.
Ability to read complex HW specifications and define a series of tests based on them.
Experience working in multi-core environments.
Experience working with real-time OS and bare metal device drivers.
Developing experience in python - advantage.
Experience with Embedded systems and driver development - advantage.
A "Can Do" attitude .
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170439
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Petah Tikva
Job Type: Full Time
The Radar VLSI team at our company EyeC is looking for an experienced Formal Verification Engineer to join us! This is a newly established team with a mission to integrate Formal Verification as a key methodology in Radar projects. Be part of a cutting-edge group designing chips for radar systems in ADAS and autonomous vehicles, where your expertise will have a significant impact.
What will your job look like:
You will verify unique and complex design blocks.
Help determine the Formal strategy and methodology for the team.
Explore new Formal methods and tools.
Requirements:
4+ years of experience in Formal Verification.
Strong debug skills.
In-depth knowledge of how Formal works.
Experience in System Verilog - Advantage.
Knowledge in Industry Standard protocols such as AXI/OCP/APB - Advantage.
Experience with multiple clock domains during cover block by Formal.
Knowledge of the following programming languages: Perl/Bash/Tcl/Python.
Experience with Hardware Verification concepts and tools (UVM).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170407
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דיווח על תוכן לא הולם או מפלה
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תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Petah Tikva
Job Type: Full Time
our company, a world leader in driver assistant systems and autonomous vehicles, is looking for silicon validation Tech Lead engineer for the range of its next generation SoCs supporting its radar systems.
Our team is responsible for validating our company's radar SoCs, utilizing Pre-Silicon environments, as well as Post-Silicon platforms.
We are developing fully embedded C++ based validation environment for our needs.
You will be taking part in developing anything from environment and drivers through system modules such as file system, network stack, memory management and more, and up to complex automation tools in both C++ and python.
What will your job look like
Get a deep understanding of our chip hardware IP blocks, both analog and digital.
Develop our validation environment.
Develop, port, or add features to the product drivers using Technical Specs and existing modules.
Define, develop and execute various complex validation scenarios on the SoC.
Debug complex SoC problems using embedded GDB, JTAG probes, going down to signal level using scopes.
Take part in Next Gen SoC's Power-On's and platforms Bring-Up's.
Collaborate with other SW/Embedded and HW/Electrical Validation teams across the company.
Requirements:
BSc in electrical engineering, computer engineering or computer science.
5+ years development experience in embedded C++.
3+ years System Validation experience.
Ability to read complex HW specifications and define a series of tests based on them.
Experience working in multi-core environments.
Experience working with real-time OS and bare metal device drivers.
Developing experience in python - advantage.
Experience with Embedded systems and driver development - advantage.
A "Can Do" attitude .
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8169117
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Petah Tikva
Job Type: Full Time
our company's EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars.
Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
Were looking for a Experienced Physical Design Engineer to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.
Requirements:
BSc or MSc degree in Computer Engineering or Electrical Engineering.
3+ years experience in the Physical Design field.
Experience with high speed interfaces (DDR/PCIE) - an advantage.
Experience with advanced nodes (5nm and below) - an advantage.
Team player with excellent communication skills, customer orientation, and a can-do attitude.
Building or maintaining implementation tools and flow - an advantage.
Experience in scripting languages like Tcl/Python/Perl/TCSH.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170498
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Petah Tikva
Job Type: Full Time
The Radar VLSI team at our company EyeC is looking for an experienced Formal Verification Engineer to join us! This is a newly established team with a mission to integrate Formal Verification as a key methodology in Radar projects. Be part of a cutting-edge group designing chips for radar systems in ADAS and autonomous vehicles, where your expertise will have a significant impact.
What will your job look like:
You will verify unique and complex design blocks.
Help determine the Formal strategy and methodology for the team.
Explore new Formal methods and tools.
Requirements:
6+ years of experience in Formal Verification.
Strong debug skills.
In-depth knowledge of how Formal works.
Experience in System Verilog - Advantage.
Knowledge in Industry Standard protocols such as AXI/OCP/APB - Advantage.
Experience with multiple clock domains during cover block by Formal.
Knowledge of the following programming languages: Perl/Bash/Tcl/Python.
Experience with Hardware Verification concepts and tools (UVM).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8170173
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Petah Tikva
Job Type: Full Time
we are looking for a Emulation Engineer to join the Radar VLSI team and drive the development of the next generation ASIC Sensors.
What will your job look like:
This role is all about making high-end Emulation environment base on new designs.
Building and integrating complex components, working with cross-functional engineering teams, and making systems that will change the way we drive.
This role requires an engineer who loves challenges and knows how to bring engineering excellence while considering complicated constraints.
You will work with members of a cross-functional talented,
You will lead the Emulation development for the VLSI team.
You will work closely with SW Engineers, Logic Engineers, Verification Engineers, and others.
You will serve as an expert matter for your domain, which has the full responsibility to drive & implement improvements and new ideas.
Requirements:
BSc in Electrical Engineering, Computer Science, or Computer Engineering.
5+ years of experience in emulation and Hands-on experience with emulation tools ( Palladium/ZeBu/Haps).
3+ of experience Designing logic (Verilog/System Verilog) , Verification (UVM) - an advantage
Hands-on bring-up and debugging of PCBs that have standard digital interfaces (e.g., SPI, I2C, MIPI)- - an advantage
Working with multiple cross-functional teams (e.g. software, Logic, Verification).
Using standard lab equipment (e.g., multimeters, oscilloscopes, spectrum analyzers).
Team player and excellent communication skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8170560
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