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We are looking for an experienced Back End Tech lead, to further develop the platform. You will join one of our Fullstack teams and help the teams build a product that customers love and use on a daily basis, a product that is fun to use, fast, reliable and scalable. The product has a broad amount of features and serves more than 1.5M active users, leading to many product and engineering challenges.
A Tech Lead is a hands-on engineer who leads by example, bridges the gap between strategy and execution, and strengthens the effectiveness of their team. This role is distinct from that of a Senior Developer through a clear set of responsibilities that focus not just on individual excellence but on team-level technical leadership, decision-making, and operational maturity.
Key Responsibilities:
Lead complex projects, own technical roadmap and architecture decisions
Actively contribute high-quality code to critical areas, set standards for the team
Drive tech standards, lead testing coverage, monitor KPIs, ensure excellence before shipping
Own platform stability, lead major incidents, drive root cause analysis and action items
Coach team through code reviews, technical sessions, and content; be the go-to technical expert
Lead the teams technical roadmap
Conduct technical interviews, run onboarding, represent team in cross-functional forums.

The System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will own the clock generation, distribution, and control logic for the entire chip - PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

This is an RTL design role, not a circuit or transistor-level design role. You will translate micro-architecture specifications into high-quality synthesizable RTL, and drive that RTL through to silicon in close partnership with the micro-architecture, Design Verification, and Physical Design (backend) teams. You will also interact with CAD, Package Design, Software, and DFT teams.

What you'll be doing:

Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out.

Defining and implementing the SOC clock and reset architecture together with the micro-architecture team - collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design.

Owning clock domain crossing infrastructure and CDC closure across the SOC.

Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power.

Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness.

Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows.

Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks.

Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable.

Supporting emulation, firmware, and post-silicon bring-up customers of your design.

The System-On-Chip (SOC) group is looking for a Senior RTL Design Engineer to serve as the technical lead for clocks development on our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will lead the development of the chip's clocking logic - PLL and reference clock integration, clock generation, distribution, muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

This is an RTL design and technical leadership role, not a circuit or transistor-level design role. Working from the clock architecture defined with the architecture and micro-architecture teams, you will lead its implementation in RTL, guide other engineers contributing to it, and drive it through to silicon in close partnership with Design Verification and Physical Design (backend). You will also interact regularly with CAD, Package Design, Software, and DFT teams.

What you'll be doing:

Acting as the technical lead for SOC clocks development - leading the implementation of the clocking logic from specification through tape-out and bring-up.

Working with the architecture and micro-architecture teams on the SOC clock and reset scheme: collecting clocking requirements from units across the chip, feeding back implementation and timing considerations, and translating the agreed scheme into a verifiable design.

Writing and reviewing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization.

Leading and mentoring other RTL engineers working on clocking: reviewing designs, setting coding and quality standards, and distributing work across the team.

Working hand-in-hand with the Physical Design (backend) team on clock tree implementation, SDC/timing constraints, partitioning, floorplan feedback, trial synthesis, and timing convergence.

Partnering with Design Verification on clocking testplans, functional and gate-level debug, and coverage closure.

Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows.

Representing clocking implementation in cross-functional design reviews with architecture, PD, DV, DFT, and CAD stakeholders.

As a chip design Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops some of the switch silicon core units

Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

Our Networking BU group is seeking to hire an expert Firmware Design Engineer for the Ethernet Switch Firmware Core team. The next generation of Switches are a crucial component of the most innovative AI and Cloud Computing Networks in the world. As a member of the Ethernet Firmware Team, you will craft and develop the firmware abstraction layer in the ETH Switch. This role will require you to participate in the design & development of firmware while working closely with hardware and architecture team to ensure timely delivery of our products to the market.

What you'll be doing:

Highly involved in the entire software development process from architecture to integration testing of firmware for the Spectrum ASIC product line.

Work with HW & ASIC team to provide insights into developing the next gen of the groundbreaking of silicon and systems.

Design and implement algorithms to improve system scale and performance.

Work with higher layer software teams to debug issues reported by customers (internal and external).

Design, implement and integrate new features according to the product roadmap.

Have a new insight on how to improve our software? Why not! Bring your ideas to life by innovating during our hackathons

Collaborate with other R&D teams around the globe.

We are looking for a senior Enterprise Account Executive to own the full sales cycle for our companys advanced financial systems with large enterprises in the United States and Europe. This is a closing role for a hunter.
You will build your own pipeline, open doors at the most senior levels of finance, and carry deals from first contact to signature. You will sell to CFOs, treasurers, and heads of finance at organizations with significant cross-border and multi-currency operations.
This is not a role for someone who waits for inbound leads. You generate the demand, you create the opportunity, and you close it.
What You Will Do
Own the entire sales cycle, from self-generated outreach through to a closed contract.
Build and run your own pipeline through proactive, targeted outbound to senior finance decision-makers.
Sell to CFOs, treasurers, and finance and operations leadership at large, complex enterprises.
Navigate multi-stakeholder, high-value deals across long, consultative buying processes.
Translate our companys advanced systems into clear financial and operational value, in the language of the finance buyer.
Represent our company with credibility and authority in front of the most senior executives.

The Networking Application Engineering team is looking for an experienced networking engineer, with wide knowledge in networking systems with focus on physical layers, to join the team and support groundbreaking technology. As a AI Networking Application Engineer one will have a real impact on the business, while working closely with our customers and R&D teams.

What youll be doing:

Gain our customers trust and understand their needs.

Support new supercomputers and AI fabrics technologies.

Solve complex issues while leading highly visible customer issues.

Work closely with various R&D teams and develop features for our customers.

Provide constructive feedback to engineering and marketing regarding products requirements.

We are looking for an experienced Team Lead for the NIC FW verification infrastructure team. In this role, you will lead the verification infrastructure - ensuring testing infrastructure stability, scalability, and continuous improvement - while guiding the development of advanced modules and methodologies. You will be responsible for driving the teams technical direction, supporting the evaluation of data and control path for new features, and ensuring high-quality deliverables that meet the expectations of industry-leading customers. As a leader, you will mentor and grow a team of engineers, foster a culture of ownership and execution, and collaborate closely with NVIDIAs networking NIC FW teams.

What you will be doing:

Lead and drive team execution end-to-end, combining managerial ownership with hands-on technical contribution - including ownership of the verification testing domain, its flows, coverage and the regression cycle.

Develop deep expertise in NVIDIA technologies, with a strong focus on FW functionality with corresponding interfaces with HW and SW.

Drive team execution by setting clear priorities, removing blockers, and ensuring high-quality, timely delivery - while maintaining a high bar for technical excellence and clearly communicating priorities, trade-offs, and status to stakeholders.

Define and continuously improve testing methodologies, including leading retrospectives for missed bugs to identify gaps - driving actionable changes to test coverage, flows, and verifiers.

Act as a technical leader within the team, contributing to design discussions, mentoring engineers, and actively participating in high-level design and code reviews.

We are looking for a talented, experienced, and passionate engineer to join the Idira EPM Agents group as a Developer. This role involves working on EPM, a combined solution for application control, privilege management, and threat detection, within a highly talented, cross-functional, agile-oriented development team. The ideal candidate will demonstrate high professional skills, a team-player mentality, and a continuous drive for new knowledge and excellence.
Key Responsibilities
Deep dive into complex system areas to analyze, propose, and build effective solutions.
Own and maintain code at the highest quality and security standards, including developing unit tests and automation.
Collaborate effectively within a cross-functional, agile development team.
Demonstrate excellent design, analytical, and problem-solving capabilities.

We are seeking an energetic and versatile Principal Software Engineer to join our elite team responsible for building our Identity Directory Service and User Management platform. In this role, you will be a core technical authority using AWS architecture, AWS CDK, and .NET to design, develop, test, secure, and deploy high throughput, production ready cloud services from planning to production.
Working in full collaboration with security architects, product managers, and cross functional development teams, you will produce complex and advanced SaaS services that satisfy demanding scalability, security standards, and Non-Functional Requirements (NFRs).
Your Impact
System Architecture & Design: Lead the architectural design and system implementation of cloud-native, distributed microservices using AWS and .NET following secure-by-design principles.
SDLC Mastery: Practice all aspects of the software development lifecycle within an agile, continuous-delivery environment.
Research & Innovation: Spearhead research into modern cybersecurity mechanisms, evaluate emerging tech stacks, and pioneer cut-edge solutions to solve complex platform bottlenecks.
Technical Mentorship: Drive engineering excellence through code reviews, design discussions, and active coaching to uplevel engineers across the team.
Quality & Scalability: Participate in continuous and iterative engineering cycles with a heavy focus on code quality, testability, supportability, performance, and cost optimization.

We are looking for an outstanding engineer to join our software architecture group and help shape the next generation of our networking products, SmartNICs, and DPUs. In this role, you will work closely with system architects, software/firmware engineers, hardware designers and product stakeholders to define component-level and system-level solutions for advanced datacenter platforms.

You will join a team working at the intersection of AI networking, virtualization, operating systems, security, management, and programmable acceleration. Our mission is to push the boundaries of modern datacenter infrastructure and help define the platforms of tomorrow.

What Youll Be Doing:

Work with architects and engineers to define software architecture for our networking devices, SmartNICs, and DPUs.

Analyze system requirements across networking protocols, virtualization, operating systems, security, management, and services.

Research new ideas, evaluate design alternatives, and build proof-of-concept models, simulations, and prototypes.

Collaborate with software, firmware, and hardware teams on HW/SW co-design, performance, scale, and resource-utilization challenges.

Learn complex datacenter technologies and turn them into clear architecture proposals, design documents, and technical presentations.

we are seeking a senior leader to establish and grow its Databricks practice. This is a unique opportunity to build and lead a strategic Data & AI capability within a leading consulting firm, shaping its vision, offerings, team, and market presence.
The role combines business leadership, solution architecture, and client engagement, helping organizations leverage modern Data & AI platforms to drive transformation and innovation.
Job description
Lead and expand EY's Databricks practice, including strategy, capability development, team growth, and go-to-market initiatives.
Design and oversee enterprise-scale Data & AI solutions, including Lakehouse architectures, data modernization programs, and AI-driven platforms.
Build trusted relationships with senior stakeholders, lead business development efforts, and drive complex technology engagements.
Lead the successful delivery of large-scale Data & AI projects while mentoring and developing high-performing teams.

We're looking for a Senior Full Stack Engineer (Frontend Oriented) to join our growing team.
Responsibilities
Design & Build modern, scalable frontend applications with React and TypeScript, delivering seamless user experiences for developers.
Develop & Maintain the design system closely with Product and UX, ensuring consistency, usability, and alignment with user needs.
Manage State at Scale using frameworks such as Redux, React Context, or React Query to support high-performance, complex applications.
Contribute Across the Stack with hands-on coding in Python and work on AWS cloud infrastructure where needed.
Collaborate closely with product, security, and backend teams to translate requirements into elegant and performant technical solutions.
Own Delivery end-to-end: architecture, implementation, automated testing, CI/CD, and production monitoring.
Champion Best Practices around code quality, documentation, accessibility, observability, and security-by-design.
Mentor & Guide teammates, sharing knowledge on modern frontend patterns and cloud-native development.

As a Senior or Principal Software Engineer in Cortex Cloud, you will contribute to the development and scaling of cloud-native security solutions for enterprise organizations. This role involves working within an established team to evolve a high-traffic product, with a focus on refining architecture, optimizing the technology stack, and maintaining engineering standards.
Your responsibilities include writing reliable code, influencing product direction, and designing distributed systems. You will be expected to make technical decisions that impact the long-term stability and performance of cloud workload protection services.
AI Integration & Engineering Workflow
A core component of our development process is the use of AI. Rather than basic code completion, we integrate AI assistants as functional components of our workflow. Our team utilizes a multi-agent AI system (IDEX/ProDex) that assists across the development lifecycle: from planning and architecture to code analysis and security reviews.
In this role, you will:
Work with AI Tools:Utilize platforms such asGemini, Claude, and Cursorfor tasks beyond code generation, including root-cause analysis, system design reviews, and architectural assessment.
Develop AI-Augmented Workflows:Help refine how AI is integrated into the SDLC, including the orchestration of agents and the development of internal tools that extend AI capabilities across our codebase.
Maintain Quality Standards:While AI assists in increasing velocity, you are responsible for the technical output. This includes critical review of all generated code and ensuring that AI-assisted work aligns with our architectural requirements and security benchmarks.
Interact with Specialized Agents:Coordinate with AI agents (Product, Architecture, Security) that operate on shared context to assist in managing complex engineering tasks.
We are looking for engineers who are interested in leveraging AI as a technical tool to manage complexity and who want to contribute to the practical application of human-AI collaboration in a cloud environment.

We are looking for an outstanding Senior Networking Software Architect to join the NIC/DPU Software and Firmware Architecture group. In this role, you will help define the next generation of our datacenter and AI networking platforms, with focus on DPU management, QoS, performance, telemetry, and software architecture across stacks. You will work closely with hardware designers, firmware/kernel driver teams, system engineers, validation, product management and customers. The role spans early architecture definition, pre-silicon design, bring-up, and production readiness for large-scale AI and cloud datacenter deployments.

What Youll Be Doing:

Own software and system architecture for next-generation DPU management, QoS, performance, telemetry, and observability features.

Define end-to-end control and management flows across DOCA, host drivers, embedded firmware, BMC, management controllers and external management systems.

Specify telemetry and observability requirements, including counters, logs, traces, events, health monitoring, debug data, and streaming telemetry.

Define management interfaces and APIs for configuration, provisioning, lifecycle operations, diagnostics, and field serviceability.

Write clear architecture specifications, interface definitions, flow diagrams, and design documents for software, firmware, and system teams.

Partner with R&D teams to translate high-level architecture into implementable designs and guide features through development, validation, silicon bring-up, and production.

Analyze system performance bottlenecks, interoperability issues, telemetry gaps, and customer-reported issues, then feed learnings into future architecture.

Collaborate with system and cluster architects to ensure NIC/DPU features fit end-to-end AI datacenter and cloud networking designs.