we are looking for a Junior Design Engineer, Google Cloud, Network
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and field-programmable gate array/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
1 year of experience architecting networking ASICs from specification to production or equivalent practical experience.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Master's degree or PhD in Computer Science or a related technical field.
Experience in the following areas: performance debugging and optimization of complex workloads, design of performance tools, compiler design and code optimization, high-performance software development techniques, concurrent programming, or multi-core computer architectures.
Experience architecting networking switches, end points, and hardware offloads.
Excellent problem-solving and debugging skills.
This position is open to all candidates.