לוח משרות דרושים מהנדס מחשבים משרה מלאה, לחיפוש זה נמצאו 157 משרות

We are seeking talented, creative and disciplined engineers to join the best-in-class team that plays a significant part in the development of new silicon for our eco-systems by engaging in a dynamic, highly collaborative environment with the focus on the following goals.

Deep understanding of components/modules within wireless communication systems and the corresponding calibration and impairment reduction techniques - Develop methods/algorithms to alleviate hardware induced impairments by calibration, cancellation and other applicable techniques - PHY firmware architecture and design, including calibrations, real-time processing flows, collaboration with RF hardware, microcode, and MAC layer.

Develop highly efficient designs delivering outstanding performance, optimizing power and memory footprints while meeting hard-realtime latency requirements.

Debug real-time systems with limited visibility, working hands-on with development boards and lab equipment.

Collaborate with Radio, MAC, and Systems engineering teams to architect, define and implement innovative algorithms, calibrations, and protocols.

Support pre-silicon validation efforts, including simulation, emulation, and FPGA prototyping.

Develop SoC test and calibration capabilities for chip, module, and product factories.

Support post-silicon bringup, validation, performance characterization, system integration and debugging. - Repeatedly measure and optimize results using various test harnesses - Automate calibration and verification processes.

We are looking for a Nitro System Manufacturing Integration Lead Engineer to be part of defining, shaping, and implementing manufacturing flows, test definitions, and card-to-server integration processes for Nitro-based platforms. This includes to be part of the manufacturing flow architecture, production test strategy, process stabilization, and yield optimization bridging system design intent with high-volume manufacturing execution.

Key job responsibilities
As a System Manufacturing Integration Lead Engineer, in the Nitro team, you will own the end-to-end manufacturing flows for accelerator card-to-server integration across manufacturing partner facilities driving the process from initial definition through stabilization into a scalable, high-yield mass production operation.

Key responsibilities include:
- Architect manufacturing flows - be part of the complete card-to-server integration sequence, including every process step, quality gate, and decision point from sub-assembly through system integration and tests.
- Define test strategy - be part of determining what to test, when, and at which station, covering card-level functional tests, post-integration validation, firmware provisioning, and first power-up diagnostics.
- Establish classification criteria - be part of determining pass/fail thresholds and test exit gates to maximize yield and minimize material waste.
- Drive process stabilization - work directly and on-site with manufacturing partners to implement, debug, and iterate on manufacturing flows from early builds through a locked, repeatable production process.
- Design alternative flows - develop parallel manufacturing paths to address real-world constraints such as component availability gaps, deferred card integration, and hub-based assembly models.
- Own process documentation & KPIs - maintain manufacturing flow baselines, drive process change control, and track yield, first-pass rate, cycle time, and defect Pareto.
- Lead cross-functional coordination - serve as the single point of ownership across hardware engineering, firmware, test/vetting, thermal, mechanical, and operations teams for Nitro-based accelerator servers built at scale.

As a Software Development Engineer in Test on our team, you will own the quality of Nitro card embedded software and firmware. You will design, develop, and maintain test automation for embedded systems and components, covering hardware interface verification, real-time firmware behavior validation, firmware update integrity, and fleet-scale deployment confidence. You will collaborate closely with firmware development teams to troubleshoot complex system-level problems at the hardware-software boundary and ensure timely delivery of high-quality Nitro card software to AWS Cloud solutions.

Key job responsibilities
- Own the firmware test automation framework - architect, develop, and extend a Python-based validation solution that scales across multiple Nitro card generations and hardware platforms, automating test coverage across the full firmware stack from boot sequences through board management layers and card-level system integration.
- Design and implement traceable, specification-driven test cases that validate firmware functional correctness, fault tolerance, and performance across hardware components, communication interfaces, and cross-subsystem interactions.
- Optimize CI/CD pipelines by integrating pre-merge and post-merge firmware validation, defining trigger policies per hardware generation, enforcing coding-standard compliance, and reducing commit-to-validated cycle time.
- Troubleshoot complex embedded system failures by analyzing firmware logs, system traces, and hardware diagnostics, then translate field incidents into targeted regression suites that prevent recurrence.
- Collaborate with firmware and hardware teams during new-generation silicon bring-up, define test plans, drive quality gates for production release, and mentor teammates on testing best practices and system architecture.

A day in the life
You start your morning reviewing overnight CI results and triaging any firmware validation failures flagged across active Nitro card generations. Mid-morning, you pair with a firmware engineer to debug a boot-sequence regression discovered during pre-merge testing, using hardware-in-the-loop test benches and system traces. After lunch, you join a design review for a next-generation Nitro card, providing input on testability and proposing validation strategies for new subsystem interfaces. Later, you refine your test framework to improve coverage for a recently released feature, then wrap up by sharing your findings in a team knowledge-sharing session.

Join our company- Migdal HaEmek we are a global leader in semiconductor innovation, developing advanced microcontroller solutions for cloud and personal computing platforms. Our products help drive secure, reliable, and resilient systems, making us a trusted partner and leading supplier in the semiconductor industry. We are looking for a talented IC TEST Engineer to join our experienced and growing team, taking part in the development of advanced semiconductor products from definition through production. What You'll Do Define, develop, and implement engineering and production TEST solutions for complex VLSI devices. Translate design specifications and product requirements into comprehensive ATE TEST plans and TEST programs. Develop, debug, validate engineering and production TEST programs for wafer sort and final TEST. Characterize IC devices Collaborate closely with cross-functional teams including Architecture, Design, DFT, Design Verification, Software, etc. Analyze TEST results, identify yield and quality improvements, and support product qualification and production ramp-up. Design and evaluate ATE hardware solutions, including Load Boards and Probe Cards. Work with external vendors and manufacturing partners to ensure successful product testing and release.

We are looking for a SQA Engineer to join our team!

Key Responsibilities:
Design, develop, and maintain automated tests for embedded products using C# and NUnit.
Execute manual and automated test plans, analyze results, and report defects.
Prepare and maintain test documentation, including STP, STD, and STR.
Investigate, reproduce, and track software defects through resolution.
Collaborate closely with R&D, software developers, and cross-functional teams to ensure product quality.
Participate in test planning, design reviews, and quality improvement activities.
Support continuous improvement of QA processes, methodologies, and automation frameworks.
Report to the SQA Team Leader.

As we expand our presence in Israel, we're seeking a visionary System Validation Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.


Job Description
The mission of this role is to perform system validation for our highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more.

You will be part of the site located at Israel (Haifa - Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your journey in our company.

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation.
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.

As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.


Key Responsibilities
Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments.
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence.
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments.
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners.
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient.

We are seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications.
In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues.
This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed.
Key Responsibilities:
Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness.
Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions.
Develop validation tests to verify functionality, performance, stability, power, and operating margins.
Debug issues across silicon, hardware, firmware, drivers, and system software.
Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces.
Develop Python scripts and automation to improve validation coverage, regression, and test efficiency.
Analyze validation data, identify issues and trends, and drive problems to root cause and closure.
Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues.
Support the transition of new silicon from initial bring-up to a qualified, production-ready product.
Operate system platforms and laboratory equipment to support validation and debug.
Document test results, issues, root cause, and recommendations and communicate findings clearly.

As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging.
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies.
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market.

System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs.
Ensure rapid cycles from RTL to functional stability through systematic debug approaches.
Own technical blocks and drive them to completion independently.

Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios.
Ensure seamless hardware-software integration for AI infrastructure connectivity.
Collaborate with Design and Verification teams to optimize emulation strategies.

As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market

System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently

Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.

We are hiring a Manager Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.

This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.

Key Responsibilities

RTL Design & Implementation
Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA.
Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality.

Cross-Functional Execution
Partner with architecture to translate specifications into implementation-ready microarchitecture.
Collaborate with verification on testplans, coverage closure, and bug triage.
Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure.

Technical Leadership & Quality
Mentor junior engineers and contribute to design methodology, scripts, and best practices.
Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments.
Drive structured, data-driven design decisions in support of aggressive tapeout schedules.

As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling our products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities
Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing.
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration).
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices.
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints.
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance.
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets.
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp.
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews.

We are looking for a Seinor Logic Design Engineer to join the ride as we spearhead the next revolution in electronics!.

Our Logic Design team builds the on-chip monitoring IP at the heart of the product - digital blocks that ship inside some of the most advanced chips in the industry. Were growing the team and looking for a Logic Design Engineer to take ownership of that logic, working alongside circuit, verification, physical design, EDA, and AE engineers. A strong fit if you enjoy hard digital design problems in a collaborative, technically demanding environment.

Responsibilities
Define and implement digital logic micro-architecture - in plain English, diagrams, and SystemVerilog.
Verify design quality against industry standards using static analysis tools (Lint, CDC, RDC).
Work with Circuit Engineers to turn low-level circuit designs into the well-behaved, insightful agents at the core of the solution.
Work with Verification Engineers to simulate and debug the digital logic.
Work with Physical Design Engineers to ensure correct implementation of our special circuits.