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We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Own the special chiplet STA, analyze the timing results, verify correctness and provide budget for the different partitions.

Generate the timing constraints for the STA and the P&R flow.

Be exposed and work on a variety of exciting designs (including high cell count and high frequency), resolving complex timing and congestion problems.

Help to shape clock tree, and effect the work of the different teams (Front end, DFT & BE).

Daily work involves all aspect of STA & chip design: take part in SDC generation & review, actively running & analyzing STA tools, guiding the group during chip closure process, etc'.

Taking part inflows development.

Take part in ramping up new breaking technologies.

We are now looking for a Senior Chip Design Engineer to join our Switch Silicon team. As a Chip Design Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What You'll Be Doing:

Work in a design/verification team which develops core units within the Switch silicon.

Micro-architecture of rtl verification environments planning for units and modules.

Design RTL of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.

RTL synthesis, timing, supporting verification, and silicon post TO activities.

Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

We are looking for a Formal Verification Engineer for our Networking team!

This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking Switch and GPU technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies that are in the heart of th AI revolution. Our team delivers world class Chips solutions for HPC, AI infrastructures, data-center, network, and storage markets. We micro-architect, verify, and deliver smart and high bandwidth multi port switches. we have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.

What you'll be doing:

In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.

You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.

You will take part in the AI revolution led by us, working on cutting edge architecture.

We are looking for an experienced HPC DevOps Engineer to help us build the supercomputers and HPC clusters of the future. As a Senior HPC DevOps Engineer, you'll be a key player in groundbreaking advancements in artificial intelligence and GPU computing. Your expertise will drive the latest breakthroughs, providing insights on at-scale system design and tuning mechanisms for large-scale compute runs. You will work with the latest Accelerated computing and Deep Learning software and hardware platforms, and with many scientific researchers, developers, and customers to craft improved workflows and develop new, leading differentiated solutions. You will interact with HPC, OS, GPU compute, and systems specialist to architect, develop and bring up large scale performance platforms.

What youll be doing:

Innovate and Implement: Design, implement, and maintain large-scale HPC/AI clusters with state-of-the-art monitoring, logging, and alerting systems.

Infrastructure as Code (IaC): Utilize and develop tools to manage infrastructure as code, ensuring scalable and repeatable deployments.

Streamline CI/CD Pipelines: Develop and maintain continuous integration and continuous delivery (CI/CD) pipelines to automate and streamline deployment processes.

Automate Everything: Develop automation scripts and tools to automate deployment, configuration management, and operational monitoring.

Enhance Monitoring: Deploy advanced monitoring solutions for servers, networks, and storage to ensure seamless operations.

Troubleshoot Complex Issues: Perform comprehensive troubleshooting from bare metal to application level, ensuring system reliability and efficiency.

Lead and Educate: Serve as a technical resource, developing and sharing best practices with internal teams.

Drive Innovation: Support R&D activities and engage in proof of concepts (POCs) and proof of values (POVs) for future improvements.

We are looking for a Formal Verification Engineer for our Networking team!

This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.

What you'll be doing:

In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.

You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.

You will learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.

We are looking for a Senior Chip-Design Verification Engineer to join our Network Adapter Silicon group. As a Senior Verification Engineer at NVIDIA Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops core units within the Networking silicon.

Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

We are looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).

Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.

Taking part in flows development and deployment.

mPrest is seeking a Lead Systems Engineer to drive the development of complex multidisciplinary projects from concept to deployment. The role involves system-level design, integration of mechanical and electrical components, coordination between engineering teams, and managing multiple parallel tasks in a dynamic environment.

Responsibilities:
Lead system engineering activities for complex, multidisciplinary defense projects
* Define system architecture, requirements, and interfaces across mechanical, electrical, and software domains
* Prepare and maintain system specifications, requirement documents, and test plans
* Collaborate with internal teams, subcontractors, and customers
* Manage risk assessments and project trade-offs
* Oversee and coordinate system integration and validation
* Participate in design reviews and lead system-level engineering discussions

Nuvoton Israel, a leading supplier of custom SoCs and security hardware solutions for the computing and servers' domain, is seeking an experienced System Validation Engineer to join our multidisciplinary R&D System & Validation group. In this role, you will be responsible for Pre and Post-Silicon validation activities, including developing chip functionality tests, building complex validation environments, and creating automated tests. You will gain deep insights into our products, encompassing both hardware and software aspects, while collaborating closely with various R&D teams.
Responsibilities: - Develop and maintain complex validation environments using Embedded C to test a wide range of chip functions - Create sophisticated automated validation tests by learning and implementing new technologies - Analyze system performance - Collaborate with cross-functional teams to ensure product quality and performance

We are looking for a DSP Engineer for development of voice processing s/w in the area of Voice over IP.
Development in C language of DSP s/w that run on many products: IP Phones , VoIP gateways, SBC and more. T
he relevant platforms are : TI DSP processors, ARM processors, Intel x86 on prem. servers and in cloud.

RT SW Developer.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the DFT Senior Engineer, you will play a crucial role in DFT Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project lifecycle, and providing sign-off DFT to tapeout.
The ML, Systems, & Cloud AI (MSCA) organization at our company's designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company's services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company's services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project - planning, execution, tracking, quality, and signoff.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Develop and execute comprehensive validation plans for our company's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools on Emulation and/or FPGA platforms.
Lead the debugging and resolution of complex silicon issues, collaborating with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.
Build and mentor a high-performing team of silicon validation engineers, fostering a culture of collaboration, innovation, and technical excellence.

About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and verification closure. You will verify digital designs and collaborate with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
The ML, Systems & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define and implement solutions for complex design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Involve in project development and convergence with the highest quality, handle issues as they arise through design and implementation.
Connect between RTL design, physical design, DFT, external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.