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Location: Haifa
Job Type: Full Time
The Design V&V Lead is responsible for managing Haifa-based V&V team members and for planning and coordinating V&V project activities.
The Haifa-based team members are part of an integrated V&V team located in Israel, the United
States, and Poland.



The V&V Lead will also support product development activities as a Test Engineer by designing and implementing detailed, comprehensive, well-structured test plans and test procedures.
The V&V Lead will need to have people management experience, as well as technical experience, including instrumentation, medical device V&V, and test method validation.
The V&V Lead should be creative and proactive to work successfully in a fast-paced environment, contributing to early prototype evaluations, test method development, design feedback to engineering teams, defect identification, and troubleshooting.



This is a full-time, exempt position located in our Haifa, Israel office and reports to the Verification and Validation Manager.









ESSENTIAL DUTIES AND RESPONSIBILITIES:

Line manager to Israel-based V&V Test Engineers and V&V Test Technicians for design verification activities.
Contribute to continuous improvements of the quality system and V&V process as part of the integrated V&V team across multiple locations.
Lead a team of different role types and varying levels of experience to perform the design V&V activities in support of product development activities.
Engage with leadership and cross-functional peers to ensure the design V&V team is integrated into the product development process, meeting both product quality and milestones on time.
Coordinate V&V activities of product development and sustaining projects.
Serve as signature alternate for V&V Manager on project-level documents, when appointed.
Execute V&V engineering work as an individual contributor when needed:
Plan test strategy and establish clear traceability between requirements and test procedures.
Analyze requirements and write test procedures with robust coverage of requirements using different test scenarios.
Write instruction-based test procedures and design test fixtures and/or SW tools as needed.
Guide and participate in the review of team members work output (above bullets) as needed to ensure a consistent quality level.
Train V&V team members on the quality system and V&V process.
Requirements:
B.S. Degree in Engineering or other technical discipline; OR Secondary school diploma, plus relevant work experience




Knowledge:

At least 5 years of medical or related industry experience in product development and/or testing.
V&V for medical device experience is preferred, or V&V in a related field with similar controls.
At least 2 years of management or leadership experience / Proven ability to manage a V&V team.
Strong verbal and written communication skills in English, including ability to give clear direction to team members.
Experience in designing, writing, reviewing, and performing design verification tests .
Experience organizing and planning test efforts.
Experience designing and creating test fixtures.
Experience in medical device product development preferred.
Familiarity with measurement uncertainty analysis and test method validation.
Demonstrated technical writing skills.
Strong grasp of fundamental engineering concepts, basic principles.
Critical thinking and decision making, including the ability to recognize when to ask questions.
Highly organized and strong attention to detail.
Capable working in a multi-disciplinary environment involving software, hardware, and mechanical engineers.
Able to work in a team environment and execute responsibilities with minimal direct supervision.
This position is open to all candidates.
 
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24/02/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Position location: in our Haifa or TLV offices, at least 2 working days at Haifa site (Hybrid model)
Responsibilities
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.
Requirements:
B.Sc. in Electrical/Computer Engineering or equivalent.
5+ years of experience as a VLSI Verification Engineer.
Expertise in System-Verilog and UVM.
Strong software development skills and the ability to develop reusable verification components and utilities.
Strong organizational and planning skills, with the ability to prioritize and drive verification projects to completion.
Effective communicator with a structured, detail-oriented approach to problem-solving and collaboration.
Advantages:

Experience with Git, Python, code templating methods, and open-source verification workflows.
Familiarity with full-chip level aspects of VLSI verification (reset architecture and sequences, power domains and modes, etc.).
Experience in firmware verification, including emulation-based verification on FPGA.
Experience with formal verification or mixed-signal simulation.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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23/02/2026
Location: Merkaz
Job Type: Full Time
we are seeking for a Verification engineer. We are seeking a highly skilled Verification engineer to join a Processor Verification team working on nextgeneration processor cores. In this role, you will take a key part in verifying critical processor blocks, collaborating closely with architecture and design teams to ensure functional correctness. You will own verification activities endtoend from TEST planning and environment development to execution, coverage analysis, and closure- using advanced verification methodologies.
Requirements:
* B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering.
* 7+ years of hands-on VLSI verification experience.
* Core Expertise: Deep knowledge of SystemVerilog and UVM (Universal Verification Methodology).
* Experience in Processors Verification (arithmetic units, control logic) is a significant advantage.
* Background in RTL Design or a strong ability to read and analyze Verilog implementation.
* Experience with C / C ++ programming is an advantage.
* Scripting capabilities ( Python / PERLgreenTxtBg!) for automation and flow efficiency.
* Strong Technical Background: You have a solid grasp of logic design principles and problem-solving.
* Independent: Capable of self-learning and driving tasks to completion.
* Ability to think creatively to find complex bugs and edge cases.
* Collaborative: Excellent interpersonal skills and a team-oriented mindset.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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