לוח משרות דרושים מהנדס וריפיקציה | ולידציה, לחיפוש זה נמצאו 74 משרות

This is an opportunity to embark on an interesting and challenging adventure into the world of satellite communication which is undergoing a major disruptive revolution.

The LS includes Control and data processing HW, SW as well as Phy and Radio HW and FW, to construct a full communication system supporting DVB-S2X as well as other Radio and IP communication protocols.

Responsibilities
Landing station system validation activity including Phy, HW and SW validation.
Study system architecture and system requirements and take part in a test plan to address these requirements in collaboration with system engineering and other teams.
Define and write automatic test plans and test procedures for new systems and features.
Build test setups for fully automated regression as well as for manual tests.
Take active part, hands-on in team execution: integration and feature/product enabling, bring up and debug activities, regression automation test of satellite systems.
Record, investigate and analyze defects.
Investigation of root cause of test case failures and providing corrective action in conjunction with development teams.
Support Test Management tools and continuous integration methodologies
Data analysis and post processing of data collected.
Compilation of regular Test execution summary report with metrics.

As a Senior RTL Verification Engineer, you will lead the verification of complex subsystems and architectural features within a next-generation, high-performance RISC‑V Application Processor. You will work closely with architecture, design, modeling, software, validation, and implementation teams to ensure first-pass silicon success while meeting aggressive performance, power, and area (PPA) targets.

In this role, you will drive verification strategy, methodology, and execution from specification through tape-out, providing technical leadership in the definition of scalable verification environments, coverage closure plans, and debug methodologies. You will be expected to independently own large verification domains, influence design and architecture decisions, and mentor junior engineers.

The ideal candidate has extensive experience in CPU or SoC verification, with strong expertise in one or more of the following areas: RISC‑V architecture, CPU microarchitecture, MMU, memory hierarchy, cache coherence, interconnects, and micro-controller verification.

Responsibilities

Lead verification efforts for complex CPU and SoC subsystems from architecture definition through tape-out.

Define comprehensive verification strategies, test plans, coverage models, and closure criteria.

Architect, develop, and maintain advanced UVM-based verification environments and reusable verification components.

Drive verification execution, including stimulus development, functional coverage closure, assertions, regressions, and debug.

Collaborate closely with architecture and design teams to review specifications, identify ambiguities, and ensure verifiability.

Develop constrained-random, directed, and scenario-based tests to validate functional correctness and corner cases.

Drive root-cause analysis and resolution of complex design and verification issues.

Define and implement verification methodologies that improve scalability, quality, and productivity across the project.

Work with software, modeling, performance, and validation teams to develop system-level verification solutions.

Analyze verification metrics and risks, proactively driving closure plans to achieve project milestones.

Mentor junior verification engineers and contribute to the technical growth of the team.

Contribute to DV methodology discussions and influence verification best practices across the organization.

we are looking for a hands‑on Design Verification Lead to drive verification of next‑generation wired/wireless peripheral subsystems that power Snapdragon platforms.

As a DV Lead in the Peripheral group, you will own verification of complex IPs and subsystems, define and execute UVM‑based verification strategy, and lead a small team of talented engineers to first‑time‑right silicon.

This is a 5 days on site position in Haifa
What youll do

Define verification strategy, test plan, and coverage goals for complex peripheral IP and subsystem blocks

Architect, develop, and maintain UVM‑based constrained‑random verification environments

Lead day‑to‑day activities of a small DV team: task planning, code and testplan reviews, mentoring, and technical guidance

Drive debug of complex issues across RTL, testbench, and system level, working closely with design, emulation and validation teams

Analyze and close functional and code coverage, drive quality metrics to tape‑out criteria

Contribute to methodology and flow improvements across the Peripheral DV team

Required V&V Engineer
Job Description Summary
Activities contributing to the design and development of products, solutions and systems. Includes activities linked to technical improvement of existing products and components Impacts quality of own work and the work of others on the team. Executes standard operational/technical tasks typically subject to instructions and work routines. There is latitude to rearrange the sequence to complete task/duties based on changing work situations.
Roles and Responsibilities:
Responsible for execution of laboratory and field validation testing, inspection and data acquisition for use in the design and validation of products and services. Responsible for design and construction of test facilities, instrumentation systems and the development of test software
Broadening knowledge of own technical discipline to execute policy/strategy. May include support roles with specialized technical field of knowledge; still acquiring higher level knowledge and skills.
Basic understanding of key business drivers; uses this understanding to accomplish own work. Good understanding of how work of own team integrates with other teams and contributes to the area.
May have some autonomy to make decisions within a defined framework. Resolves issues in situations that require good technical knowledge and judgment within established procedures. Consults more senior team members for issues outside of defined instructions/parameters.
A job at this level requires good interpersonal skills and may be required to lead a junior team. For customer facing roles, develops strong customer relationships and serves as the interface between customer and GE. Explains technical information to others.

Required Verification Engineer
Job Description Summary
Responsible for running various verification activities on PET medical products that covers multi-disciplinary aspects from SW/HW, electronics, mechanics, physics, image quality and radiation - which is safety for users and monitored by a tag all the time.
Job Description
Job Description:
Responsible for planning and implementing verification methodologies and ensuring proper fulfillment of system and sub-system requirements.
Responsible for reviewing various product designs, verifying its functionality in agile testing methods.
Responsible to determine the testing environments and tools.
Analyze and debug system failures and issue found during testing, while delivering detailed reports identifying these issues for further investigation.
Work closely with development teams
Non-hybrid, full-time position on site
Flexible on working hour, including 2-3 evening shifts (14:00-23:00) per week as needed
Working on global programs that required tight collaboration with global and Israel teams.

We are looking for an Experienced Verification Engineer for an exciting Job in its complex SoC/FPGAs, Networking and Modem verification team.
Performing Verification in the most advanced verification methodologies/tools, implementing State of the Art verification for complex ASIC.
We are looking for talented verification engineer which have abilities to own complex tasks on one hand and on the other hand be a team player, working with different vertical team and disciplines.
What Youll Do as a Part of Your Role:
Responsible for the Verification of Various IPs and top level designs.
Defining and implementing the Environment architecture from scratch.
Defining and implementing Test plans, coverage plans, etc.

Required System Verification & Validation Testing Engineer
Job Description
We are the global innovator and leading solutions provider of end-to-end wireless connectivity, specializing in transport, access, and AI-powered managed & professional services. Through our commitment to excellence, we empower customers to elevate operational efficiency and enrich the quality of experience for their end users.
Our customers include service providers, utilities, public safety organizations, government agencies, energy companies, and more, who rely on our wireless expertise and cutting-edge solutions for 5G & 4G broadband wireless connectivity, mission-critical services, and an array of applications that harness our ultra-high reliability and speed. Our solutions are deployed by more than 600 service providers, as well as more than 1,600 private network owners, in more than 130 countries.
Through our innovative, end-to-end solutions, covering hardware, software, and managed & professional services, we enable our customers to embrace the future of wireless technology with confidence, shaping the next generation of connectivity and service delivery.
We deliver extremely reliable, fast to deploy, high-capacity wireless solutions for a wide range of communication network use cases, optimized to lower TCO through minimal use of spectrum, power, real estate, and labor resources - driving simple, quick, and cost-effective network modernization and positioning Ceragus on as a leading solutions provider for the connectivity everywhere era.
System Verification & Validation Testing Engineer (V&V) - Drive end-to-end validation of complex systems and cutting-edge features. Functional and performance validation for next-gen wireless communication systems.
5G Wireless Backhaul Testing - Test and validate wireless 5G backhaul systems connecting broadband sites to the core network delivering high-speed connectivity
Codeless Automation - Design, run, and analyze automated test suites using codeless platforms to accelerate feature validation and reduce manual effort.
Failure Analysis & Debug Leadership - Lead investigations into system failures and performance issues using data-driven techniques and AI-assisted diagnostics.
Test Scenario Design & Execution - Define and execute comprehensive test plans to ensure robust functionality, scalability, and real-world resilience.
System Bring-Up & Test Setup Ownership - Build, configure, and maintain advanced test environments from the ground up
Contribute to system validating that redefines efficiency through IoT, AI integration, and advanced communication protocols.
Hybrid - 4 days onsite, 1 day remote
By joining our team, you will become a key player in our System Verification & Validation (V&V) group - where innovation meets execution.
We test the systems that power tomorrows networks: smart, wireless, and built for scale.
Also, you will enrich your experience and become a technical professional in the field of testing high-end telecommunication technology.I-POST.

We are looking for highly motivated engineers who love the challenges and the opportunity of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.