we are hiring a senior physical Verification engineer to lead signoff-quality verification for advanced silicon programs. you will drive physical verification strategy and closure for complex designs, working across implementation, methodology, and signoff teams to achieve tapeout readiness. the role requires strong technical ownership, structured debug, and the ability to scale best practices across multiple programs. this is a great match for an engineer who wants to combine technical depth with broad project impact.
what you'll be doing:
own physical verification closure for major blocks or full-chip designs through tapeout.
lead debugging of complex drc, lvs, and reliability-related issues and drive high-quality resolution.
define verification check plans, signoff criteria, and closure priorities with cross-functional teams.
partner with physical design, custom design, and cad teams to improve quality and turnaround.
drive automation, methodology improvements, and best practices for scalable pv execution.
review results, coach team members, and help reduce repeated classes of violations.
we are committed to fostering a diverse work environment and proud to be an equal opportunity employer. as we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. we will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. please contact us to request accommodation.
Requirements: what we need to see:
b.sc. or m.sc. in electrical engineering, computer engineering, or equivalent experience.
5+ years of experience in physical verification, backend implementation, or asic signoff.
deep knowledge of drc, lvs, physical signoff methodology, and tapeout flows.
strong experience with industry-standard physical verification tools and foundry rule decks.
proven ability to debug and close complex verification issues on large designs.
strong scripting and automation skills.
excellent communication and cross-team execution skills.
ways to stand out from the crowd:
experience owning full-chip pv signoff at advanced nodes.
familiarity with reliability, density, fill, erc, or other manufacturing-related signoff checks.
experience leading methodology improvements across teams.
This position is open to all candidates.