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We are looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.
Take part in the development of state-of-the-art products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the world's largest cloud provider, in a dynamic, open, and fast-paced environment.

We are looking for talented engineers to join our Chip Design team, working on the Graviton product line. Our chip design team is in charge of defining the product's features and working on their architecture and development. Our team members collaborate with multiple teams from different disciplines such as product definition, pre and post silicon validation, physical design, software and others contributing to a full cycle of chip development from idea to mass production. Your design will be integrated into the Graviton products, an important part of the AWS data centers worldwide. This is an opportunity to have a large-scale impact.

Key job responsibilities
Own a domain or sub-domain within an SoC - Take full responsibility for its entire lifecycle: Architecture and micro-architecture definition Writing RTL code in Verilog. Supporting the Verification and Emulation teams with test planning, debug, and results review Ensuring the final chip meets quality and reliability standards Collaborating with cross-functional teams - Partner with Product Definition, Verification, Emulation, Software, and Silicon Integration teams to deliver cohesive solutions.

We are looking for engineers to join our Pre-Silicon Verification team - the team that sits at the very center of the chip development lifecycle.

As a CPU Verification Engineer on the Graviton team, you will be responsible for verifying the correctness, performance, and robustness of our next-generation ARM CPU cores and their surrounding subsystems. You'll work at the intersection of micro-architecture, system architecture, and software - ensuring our CPUs meet the highest quality bar before they reach silicon.

We are looking for an experienced Firmware Manager to join the NIC Firmware team at the Yokneam site. You will take part in leading a development team in our Firmware group while taking part hands-on with development activities. The Firmware team develops cutting edge networking features for enabling the AI revolution, cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With talented engineers around the globe, the work environment is dynamic, meaningful, and fast-paced.

What you will be doing:

Lead a group of engineers and provide technical guidance and career mentorship to the team. Empower the team members to excel and increase team productiveness.

Work closely with the architecture and different software design teams.

Implement new features in the core of our NIC firmware in pre and post silicon environment.

Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.

Gain a deep understanding of system debug, networking technology and stacks, as well as the HW/FW/SW relationship.

You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed.

We are looking for a passionate Firmware Engineer to join our NIC Firmware Core team. You will be joining a team whose primary mission is to work on innovative networking adapters technologies and take the success of the current and next our networking devices to the next level using a wide range of platforms - C layer between HW and FW, C++ OOP verification environment and automation challenges.

What youll be doing:

Take part in the design, development, testing, debugging, and optimization of many angles of the network adapters' core features.

Collaborate with chip design, software, and architecture teams to define and craft legacy and new firmware flows.

Improve our team methodologies.

The Networking Advanced Development Software team develops new groundbreaking technologies to enable new market shares for the company and tighten customer relationships. These are emerging technologies in networking and distributed computing for the booming AI factories and data centers. They span areas such as AI neural networks, Deep Learning, High Performance Computing (HPC), Storage, Cloud, SW Defined Network, Network Function Virtualization, 5G NR and more. We develop the solutions top-down, all the way from application behavioral analysis, to architecture definition and down to the implementation, using the world-leading our devices. The development traverses any needed component - application SW, middleware SW, OS kernel subsystems, device drivers, embedded SW (Firmware) and CUDA GPU. We collaborate with partners and key customers in the analysis processes and engage with open source communities introducing our leading features.

What youll be doing:

Lead a team of 5 engineers in the advanced technologies development.

Design and implement solutions throughout all layers from high level application, OS and driver subsystem to firmware.

Work on impactful projects involving state-of-the-art high-performance computing hardware and software.

Provide insight and technical guidance and collaborate with peers from across the company - including software architecture, chip architecture, and engineering departments to improve our future technology.

Collaborate with our partners and customers.

We are now looking for a Senior verification technical lead for our FC Switch Silicon team. As a FullChip verification technical lead Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a FC verification team within the Switch silicon.

Dynamic verification environments planning for units infrastructures and system level.

Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

Responsible to drive the FullChip verification execution, including staging plan of the projects and deliveries.

We are building the software foundation for the next generation of AI infrastructure. As AI workloads continue to evolve, Kubernetes and the cloud-native ecosystem must evolve with them.

Our teams mission is to make Kubernetes the best platform for AI workloads. We work upstream with the Kubernetes and CNCF communities to design new APIs, build production-grade implementations, and shape the future of cloud-native infrastructure for AI.

As a Senior Software Engineer, you'll tackle the most challenging problems at the intersection of Kubernetes, distributed systems, and AI infrastructure.


What you'll be doing:

Design, implement, and upstream new capabilities for Kubernetes and CNCF projects.

Collaborate with engineering teams across us to identify AI infrastructure challenges and solve them through upstream innovation.

Work closely with Kubernetes SIGs, Working Groups, and the broader open-source community to design and implement new capabilities.

Participate in architecture discussions, API design, technical proposals, and code reviews.

Build reliable, scalable infrastructure software for next-generation AI workloads.

Write clear technical documentation and design proposals.

We are looking for an excellent, creative, and independent IC Test Validation & Automation Engineer to join our Networking unit. Our Networking has continuously reinvented itself over the years, delivering industry-leading high-speed Ethernet and InfiniBand solutions that push performance, bandwidth, and reliability from one generation to the next. In this role, you will help transfer our Network Silicon IC products, including Switch, NIC, and SmartNIC devices, from design engineering to high-quality mass production. You will define and automate IC test validation methodologies, develop validation tests and automation infrastructure, and build scalable flows for regression execution, results collection, reporting, and debug.

You will work closely with HW, SW, FW, SPE, SLT, DFT, security, and production teams, and will be responsible for improving test stability, coverage, quality, and debug visibility across wafer-level and final-test environments. The role includes troubleshooting complex test issues, improving validation methodologies, integrating tools such as Jenkins, Git, Jira, and automation agents, and acting as a gatekeeper for IC test program quality before production release. If you are passionate about IC product testing, automation, and enabling the highest-quality Networking products, we would like to hear from you.

What you'll be doing:

Definition and automation of IC test validation methodologies and procedures.

Developing validation tests and automation infrastructure.

Building Jenkins-based flows for regression execution, result collection, and reporting.

Using Git-based development workflows for test infrastructure, reviews, and releases.

Integrating Jira and MCP-based tools into validation, debug, and issue-tracking flows.

Maintaining products quality by improving test stability, coverage, quality, and debug visibility.

Troubleshooting test issues and improving automated testing methodologies.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

We are looking for best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Join accelerators IP group in Beer-Sheva, working on RiscV processor IPs.

Verification for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.

Daily work might involve any or all aspects of chip development: Verification, Design.

Work closely with Firmware and other groups around the globe.

We are looking for a best-in-class Senior Full-Chip Verification Engineer with a strong infrastructure mindset to join our Networking Silicon team. In this role, you will be responsible for the development and verification of our next-generation NICs at the system level, while also driving the evolution of the simulation infrastructure powering our verification flows. You will contribute to the architecture of high-speed communication devices by driving full-chip verification execution for the networking solutions powering the world's most advanced data centers, in a meaningful, growing environment where you make a huge impact in a technology-focused company.

What you'll be doing:

Simulation Infrastructure & Acceleration: Identify bottlenecks in the verification flow and engineer creative solutions - building frameworks, optimizing regressions, and accelerating simulation throughput through innovative tooling.

Multi-Language Development: Work across a diverse technology stack (SystemVerilog/UVM, Specman, Python, C/C++, scripting) - writing code and solving problems at every layer, from RTL testbenches to infrastructure utilities and automation.

System-Level Debug & Analysis: Gain a strong understanding of chip micro-architecture and features, investigate, debug, and resolve cross-block issues to guarantee feature correctness and compliance.

AI-Enhanced Development: Accelerate development by leveraging cutting-edge AI coding tools and frameworks - applied to both verification and infrastructure challenges.

Cross-Team Collaboration: Work closely with multiple teams within organizations such as Architecture, u-arch, Firmware and all units inside the NIC.

We are seeking a Front-End Integration Engineer for the NIC Silicon group. Join our team in our Networking business unit and be part of the innovative build and implementation of the next generation Network Adapter Silicon chips. Contribute to the development of powerful communication devices.

What You'll Be Doing:

Own and maintain Continuous Integration pipelines. Monitor, complete, and fix daily and nightly CI flows in front-end build areas. These include Lint, Synthesis, Equivalence Checking and Simulation.

Automate EDA Flows: Build, develop, and maintain robust automation scripts using Python, Tcl scripting, and Shell to integrate EDA tools (Synopsys, Cadence) into automated build pipelines.

Manage Perforce Integration: Maintain multi-IP branch/stream strategies, manage workspace specs, complete hardware build drops, and handle release labels/tags in Perforce (Helix Core).

Support Engineering Teams: Act as the primary point of contact for RTL and verification engineers to debug flow crashes, bottlenecks, environment setups, and CI failure reports.

Enforce Quality Gates: Implement automated check-in and change list triggers to run sanity checks, linting, and style enforcement before code is committed to main streams.

Optimize Infrastructure: Monitor compute farm resources (LSF) and storage usage to reduce pipeline runtime and improve overall execution efficiency.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies.
This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.
Key Responsibilities
The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.
Key responsibilities include:
Develop and support physical design CAD flows using industry-standard EDA tools
Build automation infrastructure for implementation, analysis, reporting, and debug
Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification
Create scripts and utilities to improve productivity, quality of results, and flow robustness
Support and enhance flows based on Synopsys Fusion Compiler
Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity
Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues.

We are now looking for a Power Optimization and Analysis Engineer! We prides ourselves on having energy-efficient products. We believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. As part of the u/arch team in the Switch group, you will be responsible for analyzing full chip and unit-level power data and driving the FE/BE ASIC teams to improve their units power efficiency; you will be responsible for researching, developing, and deploying methodologies to help our products become more energy efficient. Key responsibilities include developing techniques to model, analyze, and reduce power consumption of our Switches product line.

As a member of Switch u/arch Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for our next generation switches. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.

What You'll Be Doing:

Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.

Develop and share best practices for performing pre-silicon power analysis.

Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.

Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.

Select and run a wide variety of workloads for power analysis.

Prototype new architectural features in Verilog and power analysis.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.
Key Responsibilities
Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient.