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we are looking for an excellent virtual platform fw engineer to join the infrastructure and simulation integration group. in this role, you will integrate a systemc/tlm virtual hardware platform (delivered by the hardware modeling team) with firmware, make the end to end flow run reliably, and turn it into a productive environment for early development and regressions. with many hardworking engineers around the globe, the work environment is complex, driven by a passion for achieving goals, and fast paced. you will learn how large scale firmware projects are operated, maintained, qualified and released, and how firmware and pre-silicon platforms are developed together to accelerate product readiness.
what you will be doing:
work closely with firmware, hardware architecture, systemc modeling, and build/tools teams.
integrate firmware images with a systemc/tlm virtual platform and enable end to end boot, bringup, and feature flows.
define and implement hw-fw interfaces for the virtual platform (mmio, interrupts, dma, boot flows, configuration).
integrate the virtual platform flow into ci, regressions, and nightly qualification, including triage and failure analysis.
drive stability, scalability, and performance of virtual platform runs and regressions.
document processes, guidelines, and tooling that make the virtual platform easy to adopt across teams.

seeking a highly skilled and modern software engineer to develop and prototype brand new advancements in distributed training and inference using nvidias spectrum-x ai fabric. this role offers a rare chance to pioneer ai and networking technology, contributing to ground-breaking projects that will define the landscape of large-scale ai systems. improve ai app-networking connection by refining communication, crafting congestion control, coding nic firmware, and expanding switch sdk features for enhanced ai factory efficiency. your work impacts large ai system development, scaling, and speed.
what youll be doing:
prototype end-to-end solutions to improve distributed training and disaggregated inference performance.
analyze and optimize communication flows across application, transport, and network layers.
develop system software spanning communication libraries, drivers, and firmware integrations.
collaborate with hardware, firmware, and sdk teams to co-design network features.
validate and integrate prototypes into nvidias ai infrastructure and products.

we are seeking an excellent Software manager to join to nvos  sw group in yokneam ilit. you will have the opportunity to lead a development team responsible for the software of the next-generation networking products while being hands-on with development activities. we drive the data growth of the worlds biggest companies. with dedicated engineers around the globe, the work environment is dynamic, exciting, and fast-paced. are you ready for the challenge?
what you'll be doing:
lead a team of engineers and provide technical guidance to the team of highly skilled engineers. empower the team members to excel and increase team productivity.
lead the design and implementation of new features in the nvos .
drive and facilitate the planning, scheduling, and execution of the project and activities of the team
collaborate with architecture and different software design teams as part of the software development lifecycle.
support internal and external customers for any nvos related items.
gain a deep understanding of networking technology, system debugging, and stacks, as well as the sw/fw relationship.
innovate! bring our networking products to shine in the customers view

we are looking for a 100% hands-on Storage services software engineer to join the block Storage group. you will be a member of a team that builds the next generation block Storage capabilities. you will work closely with a variety of teams and architects including the networking team, and external customers. you will take part in defining the software architecture and implementation of the most advanced Storage services! services that will need to meet extreme performance and scalability demands! we have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow.
at our company, we work, think and learn as a team. we thrive in a deeply strong environment, and we're passionate about a culture that demands innovation and the highest standards. the rewards are sweet and include collaborating with some of the smartest people in the industry, an aggressive compensation plan that rewards top performers, and the opportunity to work on products that transform the way people work and play.
what youll be doing:
100% hands-on coding role in C language, Kernel and userspace
research, design, implement and TEST, new and existing, distributed Storage services and features of our block Storage solution, in both host and dpu environments.
acquire understanding of the algorithms, the technicalities and the interaction with other components across our block Storage ecosystem.
analyze and solve challenging bugs and customer cases in large scale production systems, identifying issues in our or inbox Kernel modules and often in other components. drive new solutions based on any issues that arise

our company is leading groundbreaking developments in artificial intelligence, high performance computing and visualization. the gpu -- our invention -- serves as the visual cortex of modern computers and is at the heart of our products and services. our work opens up new universes to explore, enables groundbreaking creativity and discovery, and powers inventions that were once considered science fiction, including artificial intelligence to autonomous cars. come work for the team that brought to you nccl, nvshmem & gpudirect. our gpu communication libraries are crucial for scaling deep learning and hpc applications! we're seeking a Senior Software Architect to help co-design next-gen data center platforms and scalable communications software.
DL and hpc applications have a huge compute demands and already run at scales of up to tens of thousands of gpus. gpus are connected with high-speed interconnects (e.g. nvlink, pcie) within a node and with high-speed networking (e.g. infiniband, ethernet) across nodes. efficient and fast communication between gpus directly impacts end-to-end application performance. this impact continues to grow with the increasing scale of next generation systems. this is an outstanding opportunity to advance the state-of-the-art, break performance barriers, and deliver platforms the world has never seen before. are you ready to build the new and innovative technologies that will help realize our vision?
what you will be doing:
investigate opportunities to improve communication performance by identifying bottlenecks in today's systems.
design and implement new communication technologies to accelerate ai and hpc workloads.
explore innovative solutions in hw and sw for our next generation platforms as part of co-design efforts involving gpu, networking, and sw architects.
build proofs-of-concept, conduct experiments, and perform quantitive modeling to evaluate and drive new innovations.
use simulation to explore performance of large gpu clusters (think scales of 100s of 1000s of gpus)

conduct in-depth performance characterization and analysis on large multi-gpu and multi-node clusters.
study the interaction of our libraries with all hw (gpu, cpu, networking) and sw components in the stack
evaluate proof-of-concepts, conduct trade-off analysis when multiple solutions are available
triage and root-cause performance issues reported by our customers
collect a lot of performance data ; build tools and infrastructure to visualize and analyze the information
collaborate with a very dynamic team across multiple time zones

our company is leading the way in groundbreaking developments in artificial intelligence, high performance computing and visualization. the gpu, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars.
come work for the team that brought to you nccl, nvshmem & gpudirect. our gpu communication libraries are crucial for scaling deep learning and hpc applications! we are looking for a motivated partner enablement engineer to guide our key partners and customers with nccl. most DL /hpc applications run on large clusters with high-speed networking (infiniband, roce, ethernet). this is an outstanding opportunity to get an end to end understanding of the ai networking stack. are you ready for to contribute to the development of innovative technologies and help realize our vision?
what you will be doing:
engage with our partners and customers to root cause functional and performance issues reported with nccl
conduct performance characterization and analysis of nccl and DL applications on groundbreaking gpu clusters
develop tools and automation to isolate issues on new systems and platforms, including cloud platforms (azure, aws, gcp, etc.)
guide our customers and support teams on hpc knowledge and standard methodologies for running applications on multi-node clusters
document and conduct trainings/webinars for nccl
engage with internal teams in different time zones on networking, gpus, Storage, infrastructure and support.

we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production

our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as an employee, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. come join the team and see how you can make a lasting impact on the world.
at our networking, we are driven by innovation and excellence. our team in israel is looking for a dedicated chiplet layout owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing: be part of a cross-business-unit team and own the high-speed ip integration.
build a chiplet floorplan layout design from early assembly/planning through implementation and signoff.
work closely with partition owners and full chip sta engineers to assure high quality and timely convergence.
define and implement efficient, high-quality full chip/chiplet physical design tools, flows, and methodologies.
gain hands-on experience implementing the partition-level be design (rtl2gds).

we're looking for a hardware architect for our nic and dpu division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of nvidias next generation nic and dpu products. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated debug features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system debug requirements and help define the por of our nic and dpu product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand SOC flows, pcie, ethernet, infiniband and nvlink protocols.

we are now looking for a power optimization and analysis engineer! our company prides ourselves on having energy-efficient products. we believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. as part of the u/arch team in the switch group, you will be responsible for analyzing full chip and unit-level power data and driving the fe/be asic teams to improve their units power efficiency; you will be responsible for researching, developing, and deploying methodologies to help our products become more energy efficient. key responsibilities include developing techniques to model, analyze, and reduce power consumption of our switches product line.
as a member of switch u/arch team, you will collaborate with architects, performance engineers, software engineers, asic design engineers, and physical design teams to study and implement power analysis and reduction techniques for our next generation switches. your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.
what you'll be doing:
use internally developed tools and industry standard pre-silicon gate-level and rtl power analysis tools, to help improve product power efficiency.
develop and share best practices for performing pre-silicon power analysis.
perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
interact with architects and rtl designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
select and run a wide variety of workloads for power analysis.
prototype new architectural features in verilog and power analysis.

we are looking for a formal Verification engineer for our nvidia networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking switch technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies. our switch team delivers world class bridge and router solutions for hpc, data -center, network, and Storage markets. we micro-architect, verify, and deliver smart and high bandwidth multi port switches. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of core technology.
you will work on developing new formal verification methodologies and tactics.

looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. 
what you will be doing:
join tel aviv group, working in a combined design and verification team which develops phy layer ip within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, fw and post-silicon validation.

we are now looking for a senior chip design engineer to join our switch silicon team. as a chip design engineer networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! 
what you'll be doing:
work in a design/verification team which develops core units within the switch silicon.
micro-architecture of rtl verification environments planning for units and modules.
design rtl of units/blocks according to arch. specifications under challenging constraints with high orientation to power, area, and performance.
rtl synthesis, timing, supporting verification, and silicon post to activities.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw.

lead a team of 5 engineers in the advanced technologies development
design and implement solutions throughout all layers from high level application, os and driver subsystem to firmware
work on impactful projects involving state-of-the-art high-performance computing hardware and software
provide insight and technical guidance and collaborate with peers from across the company - including software architecture, chip architecture, and engineering departments to improve our future technology
collaborate with nvidia partners and customers