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As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Technical Program Manager, you will be the key architect of our silicons operational reality. You wont just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon.

Key Responsibilities
Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors.
Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release.
Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met.
Lead process improvements across multiple teams and functions to drive better collaboration and efficiency.
Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met.
Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams.

We are seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications.
In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues.
This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed.
Key Responsibilities:
Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness.
Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions.
Develop validation tests to verify functionality, performance, stability, power, and operating margins.
Debug issues across silicon, hardware, firmware, drivers, and system software.
Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces.
Develop Python scripts and automation to improve validation coverage, regression, and test efficiency.
Analyze validation data, identify issues and trends, and drive problems to root cause and closure.
Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues.
Support the transition of new silicon from initial bring-up to a qualified, production-ready product.
Operate system platforms and laboratory equipment to support validation and debug.
Document test results, issues, root cause, and recommendations and communicate findings clearly.

As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging.
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies.
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market.

System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs.
Ensure rapid cycles from RTL to functional stability through systematic debug approaches.
Own technical blocks and drive them to completion independently.

Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios.
Ensure seamless hardware-software integration for AI infrastructure connectivity.
Collaborate with Design and Verification teams to optimize emulation strategies.

As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market

System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently

Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies

We are seeking an experienced Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems.
This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems.

This is a unique opportunity to join a new and growing Israel site, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products.

Key Responsibilities
Define and drive system and chip-level architecture for high-speed connectivity products.
Lead architecture for PCIe-based interconnects, networking protocols, and Ethernet subsystems.
Analyze system requirements and translate them into scalable and efficient hardware architectures.
Drive tradeoff analysis across performance, power, latency, area, and cost
Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering.
Define and review micro-architecture specifications and ensure alignment across teams.
Contribute to standard-based and custom protocols for next-generation AI infrastructure.
Support performance modeling, simulation, and architectural validation.
Work closely with customers and partners to understand emerging use cases and requirements.
Mentor engineers and help build strong technical leadership within the Israel R&D center.

Were hiring an AI Backend Engineering Manager to guide and grow a high-impact ML team driving AI-powered innovation across B2B SaaS platform. Youll lead the design and delivery of AI solutions while mentoring engineers and setting the technical direction for AI-first development at scale.
This is a leadership role with a balance of hands-on engineering and team management, perfect for someone who thrives on solving technical challenges, inspiring a team, and shaping the future of AI in fintech automation.
What You Will Do:
Lead & Mentor: Manage, mentor, and grow a team of AI/ML/Backend engineers, fostering technical excellence and career development.
Set Technical Direction: Define the ML strategy, ensuring best practices in architecture, frameworks, and operationalization.
Build and deploy AI-based solutions: Oversee the development and deployment of GenAI/LLM-powered solutions that address real-world challenges across products.
Scale & Operationalize: Establish scalable ML infrastructure, CI/CD, observability, and data pipelines for high-availability production systems.
Collaborate Cross-Functionally: Partner with product managers, engineers, and business stakeholders, clearly communicate progress, challenges, and outcomes.

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.

we are seeking a Full Stack Team Lead to drive AI-first development across our core platform.
As an AI-first company, we integrate artificial intelligence into every facet of our operations, from product development to internal processes. In this role, you'll lead a team of 5-6 dedicated full-stack developers, working on cutting-edge technologies to enhance user experiences and data-driven solutions.
You'll have the autonomy to make technical decisions and support other developers in a collaborative environment.
What You Will Do:
Lead Development Initiatives: Guide a team of full-stack developers in building core applications, ensuring the integration of AI-driven features.
Mentorship: Provide technical guidance to engineers, fostering their growth and promoting best practices in AI-assisted development.
Architectural Decisions: Make hands-on technical decisions for backend (Java + AWS) and frontend (React/Angular) components, incorporating AI tools where applicable.
Code Quality: Write clean, maintainable, and efficient code, setting high standards for code quality and review practices.
Cross-Functional Collaboration: Work closely with Product teams to prioritize features, estimate work, and keep projects on track, leveraging AI to streamline processes.
Innovation: Identify pain points and drive improvements in our codebase and processes, utilizing AI to enhance efficiency.
Team Motivation: Ensure daily alignment, remove blockers, and champion best practices within the team.

As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team.

This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career.


Key Responsibilities

Guided Implementation & Learning
Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place & Route (P&R), and Clock-Tree Synthesis (CTS).
Assist in macro-level implementation and develop hands-on skills in complex layout routing.
Participate in deep-submicron process challenges under close professional mentorship.

Signoff & Design Integrity Support
Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR).
Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness.
Gain exposure to the rigorous flows required to ensure first-pass silicon success.

Scripting & Cross-Functional Collaboration
Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment.
Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect.
Actively participate in team reviews and technical discussions to ramp up backend methodologies.

Were hiring a ML Engineer to accelerate AI-driven innovation across B2B SaaS platform.
Youll be at the forefront of building intelligent systems that power core product experiences and automate internal operations, driving efficiency, speed, and scale across the organization. This is a high-impact, hands-on role in a fast-growing, AI-first company where machine learning is a foundational pillar, not a bolt-on feature. You'll partner with product, engineering, and operations teams to design and implement powerful ML and LLM-based solutions that make a measurable difference.
What You Will Do:
Build Intelligent Systems: Design and develop ML/LLM-powered solutions that solve real-world challenges across product and internal workflows.
Own Full Lifecycles: Take projects from concept all the way to production, including model training, evaluation, integration, and monitoring.
Leverage State-of-the-Art Tools: Work with leading frameworks like LangChain, Hugging Face, TensorFlow, and PyTorch to deliver cutting-edge functionality.
Collaborate Cross-Functionally: Partner with product managers, engineers, and stakeholders to embed AI capabilities into user-facing features and backend services.
Ship at Scale: Build and maintain scalable APIs and services, integrating best practices in CI/CD, observability, and cloud infrastructure.
Report with Impact: Share progress, challenges, and results clearly with technical and executive stakeholders.

We are hiring a Manager Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.

This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.

Key Responsibilities

RTL Design & Implementation
Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA.
Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality.

Cross-Functional Execution
Partner with architecture to translate specifications into implementation-ready microarchitecture.
Collaborate with verification on testplans, coverage closure, and bug triage.
Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure.

Technical Leadership & Quality
Mentor junior engineers and contribute to design methodology, scripts, and best practices.
Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments.
Drive structured, data-driven design decisions in support of aggressive tapeout schedules.

we are hiring a CX Manager with deep expertise in ERP finance systems, P2P workflows, and integrations.
This role is the ERP SME and integration owner within Customer Experience. The focus is to understand how finance processes work in customer ERPs, how they connect , and how to turn customer issues, bugs, feature gaps, and new requirements into clear integration solutions.
This is a hands-on role for someone who can solve complex customer issues, define ERP integration requirements for Engineering, and lead resolution end to end. The role also operates in a highly AI-enabled environment, using AI tools, platforms and agents to improve triage, analysis, escalation management, and communication.
This role owns ERP integration within Customer Experience: diagnosing customer issues, defining integration requirements, and driving resolution end to end.
Youll partner with teams in Israel and the US and report to the Director of Customer Experience.
What You Will Do:
Own ERP integration issues across bugs, feature gaps, and customer requirements.
Serve as ERP SME and L3 support lead for complex finance workflow and integration cases.
Diagnose setup, configuration, data flow, mapping, permissions, and sync issues.
Distinguish between customer setup issues, integration issues, and product issues, and drive the right resolution path
Define functional requirements and solutions for ERP integration fixes, sync issues, missing data flows, and new capabilities.
Lead escalations with strong ownership and clear internal/external communication.
Use AI tools to improve triage, analysis, RCA, summaries, and handoffs, with clear human-review checkpoints.

We are looking for entrepreneurs with deep finance, fintech and ERP experience who bring strong product judgment.
This role is for people who have lived finance systems complexity firsthand and want to use that experience to build product. You might come from finance transformation, ERP, consulting, operations, or fintech. What matters is that you understand where workflows fall short, where controls matter, how better systems should work, and how product decisions create business value.
AI-native tools are part of how we build. This role is a chance to turn finance and ERP insight into product faster, with more context and better judgment than traditional product development allows. Youll collaborate closely with teams across the Bay Area and Israel.
What You Will Do
Find high-value opportunities in fintech and ERP workflows that should be redesigned, not just improved
Shape those opportunities into clear product direction with strong user and business value
Define workflow logic, edge cases, controls, exceptions, and handoffs
Decide what should be automated and what should remain human-driven
Work with engineering, design, data and marketing to build and ship new capabilities
Test ideas with customers, learn quickly, and refine fast
Own the path from problem identification to customer value and business impact

As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling our products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities
Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing.
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration).
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices.
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints.
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance.
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets.
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp.
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews.