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today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brain of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. come join the team and see how you can make a lasting impact on the world.
we are looking for an ai Computer Engineer to join its our company infrastructure specialists (nvis) team. academic and commercial groups around the world are using our company products to revolutionize deep learning and data analytics, and to power data centers. join the team building many of the largest and fastest ai factory systems in the world!
we are looking for someone with the ability to work on a dynamic customer-focused team that requires excellent interpersonal skills. this role will be interacting with customers, partners and internal teams, to analyse, define and implement large scale ai factory projects. the scope of these efforts includes a combination of networking, system design and automation while being the face to the customer.
what you will be doing:
primary responsibilities will include deploying, managing, and maintaining ai infrastructure for new and existing customers.
be the domain expert with customers during planning calls through implementation.
handover-related documentation and perform knowledge transfers required to support customers as they begin rolling out some of the most sophisticated systems in the world!
provide feedback to internal teams such as opening bugs, documenting workarounds, and suggesting improvements.

we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.

ethernet switch firmware team is looking for a hardworking firmware manager to take part in leading and developing the firmware / hw interface in the next generation state of the art switch products.
as a member of our fw ethernet team, you will be responsible on a team of firmware engineers. it is expected that you will manage and guide the team for critical items.
this role offers you an excellent opportunity to accomplish something new, enabling understanding of hw and sw in a rapidly growing field while solving interesting technical issues and providing feedback to the hw team to improve the next asic generation.
what you will be doing:
lead a team of engineers and provide technical guidance to the team of highly skilled engineers. empower the team members to excel and increase team productivity.
lead the design and implementation of new features in the core of switch networking firmware.
drive and facilitate the planning, scheduling, and execution of the project and activities of the team
collaborate with architecture and different software design teams as part of the software development lifecycle.
work in pre and post-silicon development environments of next-generation switch networking products.
gain a deep understanding of networking technology, system debugging, and stacks, as well as the hw/fw/sw relationship.
innovate! bring networking products to shine in customers view

we are seeking a dedicated firmware engineer to join our nic firmware core team in beer-sheva/tel-aviv. you will contribute to the development of brand-new networking adapter technologies, elevating the performance of current and future our company devices. our company develops innovative and next-generation networking devices that are known for their outstanding performance and power efficiency. the position involves all aspects of firmware development, including design, micro-architecture, software interfaces, and verification. we are seeking a dedicated and motivated engineer who will contribute to the development of advanced technology network adapters. you will also have the opportunity to create features for leading cloud computing providers and high-performance computing networks.
what youll be doing:
take a part in the design, development, TEST, debug, and optimization of low-level firmware layer on next-generation network adapters up to package release
analyze, integrate, support, and debug low-level firmware layer on verification environments
collaborate with firmware, software, and architecture teams to analyze, design, and debug legacy and new low-level firmware flow
improve our team processes including design and implementation of new methodologies, automated processes.

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of exciting designs. resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flow development.

are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our design-for- TEST engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for a dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

we are looking for best-in-class chip design engineers to join our outstanding networking silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
join beer-sheva/tel-aviv group, working on design in developing riscv core for network accelerators.
design of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
daily work will involve design and might involve any or all aspects of chip development including design and micro-architecture.
work closely with firmware, software and other groups around the globe.
work mode: hybrid home-office.

we have been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. it's an outstanding legacy of innovation that's fueled by great technology-and outstanding people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent.  youll be immersed in a diverse, encouraging environment where everyone is motivated to do their best work. come join the team and see how you can make a lasting impact on the world.
we are seeking a network security research architect who is interested in a chance to define, research, and implement next-generation security features for data centers networks. the position will take on a lead role, working with teams with varied strengths across and with external partners to research security requirements for networking products.
what you'll be doing:
lead, research, design, develop, and implement solutions for securing networks and identifying threats and incidents in the network.
apply innovative security primitives to enable secure platforms.
collaborate across external and internal hardware and software research teams.
architectural modeling, validation, microarchitectural definition, following standards bodies, and developing proof-of-concepts secure platforms.
research network telemetry for supporting secure networking platforms confidentiality, integrity, and availability.

our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. it's an outstanding legacy of innovation that's fueled by great technology-and outstanding people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as a worker, youll be immersed in a diverse, encouraging environment where everyone is motivated to do their best work. come join the team and see how you can make a lasting impact on the world.
we are seeking an experienced malware research architect who can design and implement advanced malware detection systems using virtual machine introspection (vmi) techniques. the ideal candidate should have deep expertise in developing out-of-vm security solutions that can detect and analyze sophisticated malware, rootkits, and other cyber threats by introspecting and reconstructing volatile memory states of guest operating systems and file system states. strong knowledge of file systems, and hypervisor technologies is essential. the candidate will craft automated malware detection systems that use vmi and file system techniques to predict early signs of malware execution and accurately classify unknown threats.
what you'll be doing:
lead, research, design, develop and implement solutions for next-generation secure networks.
develop novel introspection, memory forensics, and file system methods to extract critical security events towards threat detection.
collaborate with external and internal hardware and software research teams to apply extracted events for advanced malware detection.
architectural modeling, validation, microarchitectural definition, and developing proof-of-concepts secure platforms.

the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. the company system -on-chip ( SOC ) group is looking for a top asic engineer with a curiosity about SOC design automation, rtl integration, chip build and assembly, and padring design and verification. you should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
in this position, you will get the opportunity to build complex networking chips and interact directly with unit-level asic, physical design, cad, package design, software, dft and other teams.
what you'll be doing: implement chip level design through collaboration with cross-functional teams (functional design, dft, design verification, system verification, sta, and physical design).
be exposed and work on a variety of functional and structural challenges. including functional debug, physical design readiness, emulation, resolve design quality issues.
daily work involves aspects of chip level design, including partitioning, cdc, rdc, trial synthesis, design quality checks
taking part in flows development and deployment.

we are now looking for a senior ai system security architect! we are looking for an outstanding technical security architect with system architecture focus to design, validate, and guide implementation of secure architecture of its core products. the candidate is expected to: define problems and deliver highly innovative solutions that lead to significant differentiation in the industry, translate customer needs into architectural, technical & strategic direction, and help to resolve objectives & long-range goals of the security organization. leaders in this role will help reduce risk, threats, and vulnerabilities indata center products and services.
what youll be doing:
own the security requirements for networking systems in a variety of product lines.
work with technical and senior leadership staff to turn business directives into functional implementations.
collaborate between multiple business units and development groups to ensure a robust and secure product posture, from design to implementation in multiple system level products
provide hands-on security engineering expertise across a wide variety of platforms and services
provide strategic and tactical expertise in orchestrating, securing, deploying solutions; and in defining relative architectures.
this role extends across multiple groups and excellent working knowledge in the following areas of expertise is necessary for success:
designing system security architecture at hyperscale
Embedded systems security architecture and design
deep, low level understanding in root of trust (rot) technologies
networking security protocols and concepts
operating systems security and sw security concepts

our company is a global leader in control systems for our computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing 50 years ago. at qm, we provide the worlds most leading researchers and organizations with the critical tools they need to develop useful quantum computers. qms hardware and software represent a new paradigm for controlling quantum computers, from a single qubit to hundreds and thousands. we are assembling the strongest team of professionals in the world with the goal of revolutionizing how quantum computers are built and controlled and accelerating their arrival. our company is backed by globally recognized venture capital sponsors, including tlv partners, battery ventures, red dot capital partners, avigdor willenz investment group, harel insurance, and others.
we are looking for an excellent design engineer to join our team and build qm's state-of-the-art control and orchestration platform. we are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicists
responsibilities:
learning system and sw requirements for proper implementation of hw-sw interface
designing a configurable and very low-latency challenging rtl
bringing the state-of-the-art fpga to its limits with regards to logic & timing optimization
end2end ownership of the entire coding process (arch->uarch->design->implementation)

description
our company is a global leader in hybrid control systems for quantum computing, a field on the verge of exponential growth.
our innovative hardware and software offer a groundbreaking approach to controlling quantum computers, scaling from individual qubits to arrays of thousands.
at the heart of qm is a passionate, ambitious team committed to transforming the construction and operation of quantum computers. our deep understanding of customer needs drives us to deliver unmatched solutions in this revolutionary field.
we are looking for a highly experienced a hands-on compiler engineer who embodies ambition and positivity.
someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.
responsibilities:
develop qm's compiler from a proprietary quantum language to a proprietary processor tailored to realize and accelerate quantum computing.
take on complex optimization challenges at the core of our unique compiler, focusing on Real-Time applications, hybrid quantum/classical algorithms, and parallel processing.
conduct rigorous testing, debugging, and profiling to ensure the performance and correctness of compiler outputs.
hands-on development and debugging of software to optimize the utilization of limited hardware resources, enabling the scaling of quantum computing systems and improving quantum algorithm performance on our cutting-edge quantum orchestration platform.
collaborate closely with hardware, software and architecture teams to ensure seamless software-hardware integration, directly enhancing system capabilities and performance.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
collaborate with architecture, design, and verification teams to develop new product bring-up, validation, characterization, and qualification strategies, manufacturing TEST solutions for new high performance computing (hpc) products in advanced process technologies.
verify TEST solutions on pre-silicon models (simulation or emulation) and develop ate TEST modules, dc tests, binning, production flows, and characterization flows.
develop and validate TEST programs on ate platforms for new product integration (npi) in preparation for high volume manufacturing (hvm), working with ate vendors.
support product sustainability, including volume data analysis of screening and characterization data, TEST time and yield improvements, TEST escapees and return merchandise authorizations (rmas) assessments, failure localization, containment measure implementation, and partnership with design manufacturing, quality, and reliability teams to root cause and implement corrective actions.
develop tools, flows, and methodologies to continuously improve and automate the testing.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will use application-specific integrated circuit (asic) design experience to be part of a team that develops complex asic system -on-chip ( SOC ) intellectual property from proof-of-concept to production. this includes creating ip level microarchitecture definitions, register-transfer level (rtl) coding and all rtl quality checks. you will also have the opportunity to contribute to design flow and methodologies, including design generation automation. you will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing etc. you will develop/define design options for performance, power and area.the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and cloud. our end users are, cloud customers and the billions of people who use services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define the ip microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
perform rtl development (coding and debug in verilog, systemverilog).
conduct function/performance simulation debug and lint/cdc/fv/upf checks.
engage in synthesis, timing/power closure, and asic silicon bring-up.
contribute to verification TEST plan and coverage analysis of block and SOC -level.