לוח משרות דרושים הייטק תוכנה

Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
47 years of experience in FPGA prototyping or emulation of ASIC/SoC designs
Strong understanding of digital design and RTL (Verilog/SystemVerilog/VHDL).
Hands-on experience with at least one emulation/prototyping platform (Palladium, Protium, Veloce, ZeBu, or FPGA-based)
Good knowledge of synthesis, timing closure, and design partitioning for FPGA/emulation.
Familiarity with verification methodologies and environments (UVM/SystemVerilog/C).
Experience with scripting (TCL, Python, Perl, or Shell) for automation.
Strong problem-solving and debugging skills.
Ability to work in a fast-paced, collaborative environment.
Excellent communication and teamwork skills.
Preferred:
Exposure to software bring-up, driver validation, or firmware testing on emulation.
Knowledge of bus protocols (Ethernet, DDR, etc.).
Experience with debug tools (waveform viewers, logic analyzers, or emulation debug frameworks).
Background in SoC architecture and hardware/software co-design.

Requirements:
B.Sc. in Electrical/Computer Engineering, Computer Science, or Practical Engineering (hands-on IC layout/CAD experience also considered).
13 years of relevant industry experience or 3+ years for more senior candidates both junior and experienced engineers will be considered.
Hands on experience with layout and verification tools, including both commercial (Cadence, Synopsys, Mentor) and in-house CAD solutions.
Strong programming skills in SKILL, Python, TCL, Perl, and Shell (Csh, Bash).
Ability to debug, optimize, and troubleshoot CAD flows and layout workflows.
Familiarity with regression testing, code review, flow validation, and CI/CD practices in CAD/EDA environments.
Strong communication and teamwork skills, with the ability to work independently in a dynamic, fast-paced environment.
Preferred:
Prior experience as a Layout Engineer or EDA/CAD Physical Design Engineer in a semiconductor environment.
Deep understanding of IC physical design and verification flows:
Custom analog/digital layout, floorplanning, placement, routing
DRC, LVS, ERC, parasitic extraction
Physical verification and tapeout readiness
Advanced SKILL programming for layout automation and productivity.
Experience with tapeout preparation, design rule integration, and physical verification.
Knowledge of PCells, parameterized devices, and layout generators.
Proficiency in physical verification runset programming and maintenance, including customization of DRC/LVS/ERC decks and integration into design flows.
Experience building automated regression environments for CAD/EDA flows in SKILL.
Experience with in-house CAD tool development and with the integration and customization of both in-house and commercial solutions.

Requirements:
8+ Proven experience in bring-up and productization of complex ICs
Proficiency in C/C++ /VBA scripting languages (e.g., Python, Perl) in a Unix environment
Strong analytical skills and experience in yield/data analysis using tools like JMP
Familiarity with test platforms such as Teradyne UltraFlex/UltraFlexPlus a strong advantage
Experience working with external test and assembly houses (OSATs)
Knowledge of Verilog and RTL simulations a plus
Excellent communication skills, strong ownership, and a proactive, team-oriented mindset

Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering
8+ years of VLSI experience.
Experience with multi clock domain, multi power domain designs (UPF).
Methodologic approach.
Strong Motivated to learn quickly, hard-working, and is results-oriented.
Great interpersonal relations skills.
Preferred:
Networking design experience Major Advantage
Backend experience: STA tools, formal equivalence tools, frontend/backend handoff methodologies.
SoC design/Integration experience.
Proven Methodologies and Environmental Building Experience.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.

Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
8+ years experience in full chip design.
Experience in leading the full-chip level design and successfully taping out multiple intricate SoCs.
Experience in floor planning, integration, signoff methodologies, and signoff tools for hierarchical designs.
Experience with SoC design practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
Expert knowledge of the entire backend design flow from RTL to TO.
Experience with STA (Static Timing Analysis) tools like primetime or tempus.
Experience with IR drop tools like Ansys Redhawk or Volta's.
Physical Verification Expert (DRC/LVS).
Strong independent and motivated to learn quickly, hard-working, and is results oriented.
Good social skills and ability to work collaboratively with other teams.
Preferred:
Experience with high-speed serial interfaces such as PCIe, DDR, Ethernet.
Familiarity with advanced DFT flows & tools.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.

Requirements:
B.Sc. in Electrical/Computer Engineering, Computer Science, or Practical Engineering, or equivalent hands-on IC CAD/EDA experience.
Hands-on experience with physical design and verification tools, including both commercial (Cadence, Synopsys, Mentor) and in-house CAD solutions.
Strong programming skills in SKILL, Python, Tcl, Perl, and Shell (Csh, Bash).
Ability to debug, optimize, and troubleshoot CAD flows and physical design workflows.
Familiarity with regression testing, code review, flow validation, and CI/CD practices in CAD/EDA environments.
Strong communication and teamwork skills, and the ability to work independently in a dynamic, fast-paced environment.
Preferred:
Prior experience as a CAD/EDA Engineer or Physical Design Engineer in a semiconductor environment.
Deep understanding of IC physical design and verification flows:
Floorplanning, placement, routing, power, and clock distribution
DRC, LVS, ERC, parasitic extraction
Physical verification and tapeout readiness
Advanced SKILL programming for automation and productivity.
Experience with tapeout preparation, design rule integration, and physical verification.
Knowledge of PCells, parameterized devices, and flow generators.
Proficiency in physical verification, runset programming, and maintenance.
Experience building automated regression environments for CAD/EDA flows.
Experience with in-house CAD tool development and with the integration and customization of both in-house and commercial solutions.

Requirements:
Bachelors or Masters degree in Computer Engineering, Computer Science, or equivalent
5+ years of experience developing modern C++ (14/17/20) applications in embedded/Linux environments
Proven track record of owning large, complex codebases
Expertise in multithreading and real‑time systems
Strong background in software architecture and design
Excellent problem‑solving skills, with clear written and verbal communication
Hands-on, proactive, and comfortable working independently and cross-functionally
Preferred:
Proficiency with Git workflows, build systems (CMake), and debugging tools
Prior work on ASIC‑based products
Familiarity with hardware communication protocols: SPI, I²C, GPIO
Experience with safety‑critical systems, system profiling, performance tuning or thermal optimization