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we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities


Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.


Key Responsibilities


Develop and maintain automated flows for Synthesis, Place & Route (P&R), and Floor-planning to ensure seamless design transitions
Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints
Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations
Own the design database structure and version control to ensure team alignment and data integrity
Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results
Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing

we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities


Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

we're seeking a visionary Staff Physical STA Expert to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the sign-off methodology for chips that power the world's most advanced AI clusters.

As a Staff Physical STA Expert , you will hold the keys to silicon success. You will be leading the STA activities end-to-end from Chip partition, Time budgeting through signoff of all the chips we develop. You will build and lead the STA team to run several chips signoffs in parallel. In addition, You will define the sign-off methodology for chips that power the worlds most advanced AI clusters. You will act as the central nervous system of the design process, bridging the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities

Take full ownership of the STA flow and sign-off methodologies. You will establish the rigorous criteria that ensure our products succeed in the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams. You will lead timing reviews and work closely with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints from the ground up, ensuring they are robust across multi-scenario environments
Tackle the challenges of cross-chip clock distribution networks and sophisticated margining techniques, ensuring robust silicon across all process corners
Have a passion for better workflows? Youll participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and in-house automation to make our sign-off process faster and smarter

Required Antenna System and RF Engineer
Overview:
Antenna system and RF engineer that will primarily lead antenna system design, testing and system verification from concept to production.
The position is part of the RF R&D team and will require in addition RF board design and testing.
Responsibilities will range from initial concept stage up to production including concept verifications, guiding mechanical design, final product approval including outdoor testing and transfer to production.
The designs require multi discipline knowledge in antennas, antenna arrays, mechanics, RF and system considerations
The job requires collaboration with the system, electrical, mechanical, software, manufacturing, and system test engineers to ensure successful product design and transition to production.

We are looking for a highly skilled RF Test Automation Developer to join our R&D Integration Automation team.
This role is focused on designing, developing, and maintaining advanced automation solutions across unit, integration, system, and end-to-end testing levels.
The ideal candidate is a hands-on developer with strong expertise in Python and Pytest, experienced in building and executing automated tests, and comfortable working with modern CI/CD pipelines and automation tools.
The Senior Developer will act as a technical mentor and key contributor, ensuring best practices are followed and test automation is seamlessly embedded into the development lifecycle.
Knowledge of RF systems is a strong plus.
Key Responsibilities:
Develop and maintain automated RF test development tools using Python and other relevant programming languages.
Configure, calibrate, and operate RF test equipment such as Vector Signal Generators (VSGs), Spectrum Analyzers (SAs), and related instruments.
Create and validate RF test setups for performance validation, debug, and system characterization.
Analyze test results, generate comprehensive reports, and present findings to cross-functional teams.
Collaborate with hardware and software engineers to integrate automated RF testing into the product development cycle.
Stay current with emerging RF technologies and testing methodologies, proposing and implementing improvements to existing test processes.
Contribute to the development of RF testing strategies aligned with R&D goals and product roadmaps.
Research and introduce innovative RF automation tools, frameworks, and workflows aligned with R&D goals.

Required Hardware Debug Technician/Engineer
Role responsibilities:
Final tests technician (Hands-on) in Production line
Manage HW testing in production, Line setup, Calibration and Maintenance
Deep HW knowledge in RF & Digital
Functional testing of electronic circuits according to specifications.
Overall responsibility for debug & analysis in boards & System level
Responsibility repair, analysis and documentation
ATE stations technical support.

As an xEngineer in the Automations team, you'll play a pivotal role in shaping the company Automations platform, used by millions of users and various internal and external applications. Your work will directly impact the revenue of both our company and our users.
In your day-to-day, you will:
Take projects from ideation to production, including technical design, coding, and beyond
Design and build scalable backend systems using modern technologies and best practices
Participate in designing APIs, mechanisms and abstractions for the Automations platform
Develop new solutions and improve existing ones in areas such as production, testing and performance
Collaborate closely with a highly experienced team.

We are seeking a highly skilled and motivated Technical Writer to join the Education Teams effort in auditing, revamping, and creating content for our customer-facing Help Center/Knowledge Base. This role is critical as the quality and structure of the documentation will directly feed and train our new AI support tools and directly support our customers.
our Education team members have a deep desire to fully understand complex concepts, then be able to break them down to present them in a well-structured yet simplified and engaging manner.
The ideal candidate will be a strategic thinker who is a team player and an educator at heart, passionate about technology, with a deep understanding of technical documentation standards, information architecture, and the specific requirements for AI-ready content, training and education methodologies.
Responsibilities:
Knowledge Base Revamp & AI Optimization:
Conduct a comprehensive audit of the existing Help Center content for accuracy, clarity, completeness, and consistency as we migrate to a new tool.
collaborate and maintain a new information architecture and content structure optimized specifically for ingestion and utilization by AI support tools (e.g., clear, concise articles, defined topic boundaries, robust tagging/metadata).
Collaborate with the AI/Engineering teams to understand the technical requirements for content delivery to the AI platform and establish content governance rules.
Content Creation and Management:
Write, edit, and publish high-quality, user-friendly technical documentation, including tutorials, how-to guides, troubleshooting steps, and feature overviews for our SaaS product.
Understand target audiences to be able to accommodate the different roles and personas.
Ensure all content adheres to our brand voice, style guide, and technical accuracy.
Manage the documentation lifecycle within the chosen Knowledge Base platform (Confluence, Intercom).
Cross-functional Collaboration:
Work closely with Product Managers and Engineers to document new features and updates before launch, for both internal and external users.
Partner with the Customer Support team to identify key pain points and knowledge gaps that can be addressed by improved documentation and AI routing.
Provide feedback to the product team on UI/UX improvements based on content structure and user confusion.
Metrics and Improvement:
Establish and track key performance indicators (KPIs) related to documentation effectiveness, such as content usage, search success rates, case deflection rates attributable to the AI, and content quality scores.

Product Analytics aims to help developers, product managers and designers understand their users, take data-oriented product decisions and evaluate the impact of technical issues on their customer base. As a Senior Software Engineer on the Product Analytics Backend team, you'll join a new, fast-growing product area. You will help define our technical vision, influence the product roadmap, and solve complex engineering challenges at scale.
In Product Analytics, we consume and process data from multiple sources: clickstreams, user information, and data from third-party systems. Your work will be central to building a robust and flexible system that can ingest, manipulate, correlate and store all this data to have it efficiently queried by our end users.
At our company, we place value in our office culture - the relationships that it builds, the creativity it brings to the table, and the collaboration of being together. We operate as a hybrid workplace to ensure our employees can create a work-life harmony that best fits them.
What Youll Do:
Design, build, and maintain core backend systems for Product Analytics, ensuring scalability, reliability, and high performance
Drive technical architecture decisions in alignment with product goals and collaborate closely with frontend and platform teams
Work with our core platform teams to tailor our company's storage and query solutions to our needs
Create a strong team culture aligned with our engineering standards and our customer focus
Participate in hands-on engineering work including coding, code reviews, and design reviews.

That's why we're hiring a sharp, AI-enthusiastic technical writer and content creator to own how we produce, automate, and scale our documentation and content. You'll sit at the intersection of technical writing, product marketing, and AI automation - managing our knowledge base, building AI-powered workflows, and partnering with PMM to produce high-quality content at scale. If the idea of using AI to 10x a content team's output without sacrificing quality excites you, keep reading.


Responsibilities:
What You'll Do

Documentation & Knowledge Base

Own and maintain documentation - ensuring it is accurate, well-structured, and always up to date

Write and edit technical documentation including product guides, release notes, API references, onboarding materials, and FAQs

Build a scalable documentation system that can grow with our product and team

Work closely with Product and Engineering to translate complex technical concepts into clear, accessible content

AI Automation & Workflow

Design and implement AI-powered workflows to automate repetitive documentation and content tasks

Use tools like LLMs, AI writing assistants, and automation platforms to accelerate content production

Build prompt libraries, content templates, and AI-assisted review processes that maintain brand quality

Identify new opportunities to use AI to improve content accuracy, consistency, and speed

Content Creation for PMM

Partner with the Product Marketing team to create content, including blog posts, case studies, landing page copy, product one-pagers, and email sequences

Help maintain brand voice across all content types - from technical docs to marketing material

Support campaign launches with well-written, technically accurate content that speaks to both technical and business audiences

Want to get your hands on our cutting edge Switching technologies? Switch Firmware team is looking for a Senior Firmware engineer to take part in the architecture definition of the Firmware / HW interfaces of next generation state of the art Switch products.
What you'll be doing:
As a Firmware engineer in the position of micro-architecture, you will work closely with the various chip design teams and define the Firmware architecture for all the features developed in the Firmware team. This role offers you an excellent opportunity to accomplish something new, enable deep and thorough understanding of the HW and Firmware in a rapidly growing field while solving exciting technical issues for improving next ASIC generations.

We are seeking to hire an excellent Firmware Engineer to join the GPU networking (NVLink) FW group in Tel-Aviv / Raanana. You will have the opportunity to take part in designing, implementing, and driving major development firmware features, delivering the next-generation GPU networking products.
We drive the data growth of the worlds biggest companies. With dedicated engineers around the globe, the work environment is dynamic, exciting, and fast-paced. Are you ready for the challenge?
What you will be doing:
Design and implement new features in the core of our GPU firmware.
Collaborate with architecture and different software design teams throughout the software development lifecycle.
Work in Pre & Post-silicon development environments of next-generation GPU products.
Gain a deep understanding of system debugging, networking technology, and stacks, as well as the HW/FW/SW relationship.
Innovate! Bring our FW switching products to shine in customers view.
Collaborate with other R&D teams around the globe.

We are looking for an experienced Firmware Manager to join the NIC Firmware team at the Yokneam site. You will take part in leading a major development team in our Firmware group while taking part hands-on with development activities. The Firmware team develops cutting edge networking features for enabling the AI revolution, cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With talented engineers around the globe, the work environment is dynamic, meaningful, and fast-paced.
What you will be doing:
Lead a group of engineers and provide technical guidance and career mentorship to the team. Empower the team members to excel and increase team productiveness.
Work closely with the architecture and different software design teams.
Implement new features in the core of our NIC firmware in pre and post silicon environment.
Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.
Gain a deep understanding of system debug, networking technology and stacks, as well as the HW/FW/SW relationship.
You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed.