לוח משרות דרושים Senior V&V משרה מלאה

our eyeq platform group (epg) is seeking a motivated formal Verification engineer to join our team and contribute to development of hardware verification environments.
this position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
this is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle. what will your job look like:
be the owner of formal verification environment from first draft to sign-off stage
apply formal methods to verify the correctness of various complex digital systems
work with hw architects/designers to define assumptions, rules and cover properties
help define the formal verification methodology and environment to be applied by the team
explore new formal methods and tools
work with tools like cadence jaspergold, verisium manager, xcelium, indago
analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
develop generic formal blocks/functions of commonly used logic, to be later used off the shelf

we are looking for a talented, fast learner, and highly motivated chip design - Verification engineer. as a member of our chip design team, you will be responsible for verifying portions of the design, of a high performance and low power chip, focusing on such tasks as micro-architectural understanding, verification environment coding and logic debug. this position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines roadmap. we have crafted a team of extraordinary people, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
what you'll be doing:
as a member of our chip design team, you'll own and be responsible for crafting and timely delivery of a verification components and quality of chip design related logic. day to day tasks include:
understand and analyze uarch definitions.
implement verification components to verify rtl meets specifications.
collaborate with our rtl, arch and uarch teams.
work on logic related to switch design.

we are looking for an excellent highly motivated senior SW engineer with experience in Embedded software development to join the software testing team in the data processing unit (dpu) sw group. we are looking for a candidate with the ability to thrive in an environment with complex software and hardware designs, take ownership and lead the sw testing of key components of the dpu. the role includes working closely with hw, fw, and sw teams all over the world, and take our product to next level. 
what youll be doing:
build automated verification environment for high-end hardware and software which is at the forefront of innovation
develop and maintain TEST automation frameworks and scripts using Python
identify, analyze, and report software defects, inconsistencies, and other quality issues
make better product quality by improving tests coverage
take an active part in development, integration and verification with r&d
drive improvements for performance, quality, stability around sw acceleration solutions
stay up to date with industry best practices, new technologies, and emerging trends in software verification

our company is a global leader in control systems for computing, a field on the verge of exponential growth. our innovative hardware and software mark a groundbreaking approach in our computer control, scaling from individual qubits to expansive arrays of thousands.
at the core of qm lies a passionate and ambitious team committed to reshaping the construction and operation of our computers. our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
we are looking for a Verification engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base.
the Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and our physicists.
responsibilities:
practicing the full range of verification aspects
creating a verification environment from scratch (drivers, monitors, coverage...)
vip (ddr/pcie/axi) integration
defining verification sequences via a complex control-flow constraint set
system understanding of a Full-Stack product with strong hw-sw coupling
reference model integration
TEST plan definition
defining verification flows and creating the proper infrastructure to support it

our company is a global leader in control systems for our computing, a field on the verge of exponential growth. our innovative hardware and software mark a groundbreaking approach in our computer control, scaling from individual qubits to expansive arrays of thousands.
at the core of qm lies a passionate and ambitious team committed to reshaping the construction and operation of our computers. our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
we are looking for a Verification engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base.
the Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and our physicists.
responsibilities:
practicing the full range of verification aspects
creating a verification environment from scratch (drivers, monitors, coverage...)
vip (ddr/pcie/axi) integration
defining verification sequences via a complex control-flow constraint set
system understanding of a Full-Stack product with strong hw-sw coupling
reference model integration
TEST plan definition
defining verification flows and creating the proper infrastructure to support it

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, and system testing, and drive verification closure. you will verify digital designs, collaborate closely with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. you will manage the full life-cycle of verification, which can range from verification planning and TEST execution to collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower our customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include, cloud customers, and billions of our users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog and uvm, or formally verify designs with systemverilog assertions (sva) and industry leading formal tools.
identify and write all types of coverage measures for corner-cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.

Required Senior Formal Verification Engineer (Contractor)
Role Description
This is a full-time on-site role for a Formal Verification Engineer in Petah Tikva, Israel.
The Formal Verification Engineer will be responsible for developing and implementing formal verification environments, writing and applying verification plans, and conducting formal property verification. Additional tasks include analyzing coverage results, debugging, working with design engineers to resolve issues, and reporting outcomes to ensure the accuracy and efficiency of the designs.