We are looking for a Verification Engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base.
The Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists.
Responsibilities:
Practicing the full range of verification aspects
Creating a verification environment from scratch (drivers, monitors, coverage...)
VIP (DDR/PCIe/AXI) integration
Defining verification sequences via a complex control-flow constraint set
System understanding of a full-stack product with strong HW-SW coupling
Reference model integration
Test plan definition
Defining verification flows and creating the proper infrastructure to support it.
Requirements: At least 5 years experience.
Ability to ramp up verification environments from scratch
Experience with UVM, System Verilog - Advantage
Knowledge of Verification IPs and protocols (PCIe, DDR, AXI)
Good understanding of HW/SW interaction- Advantage
Knowledge in C/C++/Python/System C - Advantage.
This position is open to all candidates.