לוח משרות דרושים ניהול - חשמל / אלקטרוניקה משרה מלאה

We are looking for a Senior Core Power Management Architect.
Job Description:
Will drive the implementation of autonomous core power management for best performance and power efficacy.
The Power expert will take charge in understanding business-units (customers) needs, and translate them to CPU core solution.
This expert will utilize his power management experience to deliver world-class power efficient HW-SW solutions for Huawei products.
Responsibilities:
Responsible for bringing Huawei CPU to a leading position in Performance-Power efficiency.

A problem isnt truly solved until its solved for all. Thats why our customers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at our company, youll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. Youll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers.
As a Technical Program Manager for Silicon Development, you will use your technical and management experience to lead the development and execution of complex, multidisciplinary SoC projects. You will plan programs and manage their execution from early concept through development to tapeout and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life-cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan, coordinate, and deliver custom silicon products.
Assess complexity and scope out the project, generate task lists, build an efficient and effective project timeline and work with the teams to make it reality.
Lead the creation of credible and data-driven schedules and milestones, track the progress, proactively identify potential future issues, and identify mitigations with the various team leaders.
Drive technical, budgetary, and schedule trade-off discussions with cross-functional teams, balancing what is needed with what is possible.
Manage project execution and issues as they arise through design, development, test, manufacturing, deployment and sustaining activities for silicon and hardware products.

Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.

Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Lead the development of flows & methodologies from Synthesis, Place & Route & All signoff flows.
Plan & execute flow releases, coordinate & track development tasks between the team.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Serve as the technical lead while mentoring and guiding team members.

Required VLSI Logic Design Technical Lead
The EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.

Were looking for a talented and driven Integration Team Lead to join our System Engineering group. In this role, youll lead the integration team, working closely with system engineers, V&V, and other R&D functions to bring cutting-edge technologies into reality.

Responsibilities:
Lead and manage the integration team, including task planning, setting priorities and mentoring team members.
Be the technical focal point for integration-related activities
Oversee system testing and manage the handover process from Integration to V&V.
Lead system bring up activities.
Responsible for troubleshooting efforts and resolving problems in a timely manner.
Maintain a broad understanding of the entire system and stay up to date with the latest version.
Lead by example, motivate, empower and develop team members to reach their full potential.
Establish strong working relationships with System Engineering and V&V teams to ensure high-quality delivery.
Collaborate closely with multiple cross-functional teams across the organization.

We are looking for a highly experienced and motivated VLSI Manager to lead the development of our next-generation ASICfrom initial concept to final production. In this pivotal role, you'll manage the entire ASIC development lifecycle, working closely with cross-functional teams and external partners to deliver cutting-edge technology that powers the future of autonomous vehicles.

Responsibilities:
Own and lead the end-to-end ASIC development process.
Act as the central point of contact for all ASIC-related activities, collaborating with Product, Firmware, Computer Vision, Hardware, and other stakeholders.
Drive the ASIC program work plan, ensuring alignment and coordination across global teams and multiple workstreams.
Define and enforce VLSI development methodologies, design flows, and quality standards.
Evaluate and select both digital and analog IPs required for the ASIC.
Manage relationships and deliverables with external VLSI partners and service providers, ensuring high-quality outcomes.