לוח משרות דרושים ניהול - חשמל / אלקטרוניקה משרה מלאה, לחיפוש זה נמצאו 86 משרות

As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and run-set development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Also, you should have worked with Dummy Metal Fill generation and Design for Manufacturability (DFM) rules at different technologies.
Responsibilities
Develop, improve and maintain all aspects of physical verification flow and methodology
Coordinate the effort of validating flows, improving for custom checks and data generation
Work with the design and PD teams to facilitate the chip design process
Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
Collaborate with tool vendors and foundries for PDK performance enhancements

we are looking for a talented and experienced design manager to drive and help our group to get to the next era of computer architecture. In this position, you will design the critical parts of future chips. You will be involved in the full design cycle from architectural requirements into micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.



Responsibilities
Be accountable for your team's milestones & timelines
Leading your team members and developing their abilities
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators, monitor and report execution progress to enable prioritization and clear decision-making
Acquire the system Architecture and be part of the leading technical FE forum

we are looking for a talented and experienced Physical Design lead to take part in the physical design and help lead the companys BE activities . This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on our final product

Responsibilities


Lead blocks and sub systems execution from RTL to GDSII.
Clearly reflect status and execution metrics and help identify and solve execution bottlenecks.
Spec and define full floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet PPA targets.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip

Come help lead the design and development of one of the most ambitious products at the forefront of compute technology!

Responsibilities
Lead a physical design team responsible for all stages of the physical design process-floor planning, placement, clock tree synthesis, routing, timing, and power optimization at both block and subsystem levels.
Mentor and guide a team of physical design engineers through all stages of the design flow.
Collaborate closely with project managers and other technical leads to ensure timely delivery and successful completion of projects.
Drive the technical direction of the physical design process to ensure efficient, high-quality outcomes.
Develop and implement best practices for physical design and continuous improvements of design workflows.
Optimize designs for performance, power, and area (PPA) to meet project goals.
Ensure compliance with DRC (design rule checking) and LVS (layout versus schematic) requirements. .
Drive timing analysis and closure, working closely with the RTL design team to resolve timing violations.

we are looking for a talented and experienced engineer to participate in designing the next era of computer architecture. In this position you will take part in designing the critical parts of future chips. You will transform architectural requirements to micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.

Responsibilities
Define and drive the design of advanced blocks from micro-architecture phase to netlist
Support timing and constraints definitions work closely with the BE team on timing and physical implementation efforts
Leading processes relating to power optimization
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making

we are looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.

Responsibilities
Generate and analyze critical block- and chip-level static timing constraints
Spec and define full chip floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet timing, area, and power constraints
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip integration

We seek an AIR SaaS Platform Verification Manager to join our Air - the Data Center Digital Twin. As a AIR SaaS Platform Verification Manager, you will have to work closely with our development and architecture teams responsible for our Air and gain a deep understanding of our products and technologies. and gain a deep understanding of our products and technologies.


What youll be doing:
Leading and managing the verification team responsible for AIR SaaS Platform, ensuring high quality delivery of both the backend and the frontend, working closely with diverse cross-functional teams to effectively implement, improve and automate verification strategies for cloud and on-prem deployments.
Work with the DevOps to integrate the verification pipeline into the CI/CD and use your expertise in Python and frontend testing to identify the most effective verification methodologies and tools, suggest reporting process improvement.
Analyze customer-reported issues, identify test gaps, and ensure robust regression coverage.
Foster a culture of innovation, quality, ownership, and accountability.
Support team members with career development plans and achievable growth goals.
Drive improvements for performance, quality, stability around SW acceleration solutions.
Stay up to date with industry standard methodologies, new technologies, and emerging trends in software verification.

SolarEdge (NASDAQ: SEDG) is a global leader in high-performance smart energy technology, with over 3000 employees, offices in 34 countries, and millions of products installed in over 133 countries. Our diverse product offering comprises intelligent solar inverters, battery storage, backup systems, EV charging, and complete home energy management ecosystems. By leveraging world-class engineering capabilities and with a relentless focus on innovation, we strive to create a world where clean, green energy from the sun is the primary source of power for our homes, businesses, and just about everywhere we thrive. We are looking for an experienced PCB Layout Designer to join our Layout Design team within the SolarEdge Hardware division. The Layout Design team is responsible for the layout of all core Hardware products, including High-Voltage power boards, optimizers, communication circuits, and complex battery management systems (BMS). This is a highly challenging role where you will work in a dynamic, fast-paced environment, handling multiple priority projects under tight schedules while working closely with Hardware, Q&R, and Mechanical engineers. What you will do:
* Design and develop multi-layer PCB layouts from concept to production, including placement, routing, and final manufacturing outputs.
* Translate schematics into optimized layouts considering Signal Integrity (SI), Power Integrity (PI), EMI/EMC mitigation, thermal, and manufacturability constraints.
* Work in a Cadence Allegro and OrCAD Capture environment, including the use of parallel layout tools like Symphony to accelerate delivery.
* Collaborate closely with Mechanical engineers (handling 3D IDF/IDX transfers), R&D teams, and Reliability (Q&R) teams to meet strict mechanical constraints.
* Strictly adhere to our internal "Design Considerations" guidelines and the team's layout "Cookbook" methodologies to ensure standardized execution.

Country:
Israel

City:
Herzliya