לוח משרות דרושים ASIC / VLSI בתל אביב יפו

Required DFT/Synthesis Design Engineer
Responsible for writing timing constraints, running synthesis and implementing DFT (including scan, MBIST and IP testing), you will work on our next generation 5G IC and interact with software, signal processing algorithms, integration and layout teams.

Required ASIC Design Engineer
Within the BBIC team, you will be responsible for the specification, design and validation of various modules linked to our next chipsets generation.
You will work closely with our other teams (software, signal processing algorithms and integration).
RESPONSIBILITIES
Micro-architecture definitions at the unit level
Specification, design, RTL coding and optimization of complex blocks
Close work with the verification team on block/top level to ensure timely delivery of quality designs.

Required ASIC Verification Engineer
Verification Group in a growing group responsible for pre-silicon ASIC Verification of complex chips implementing an advanced modem technology.
As part of the role, you will architect, develop & own blocks / sub-subsystem / system-level verification benches. You will be a major contributor to advanced SV UVM methodologies and to infrastructure development. You will be part of an advanced development flow, using state-of-the-art development & Verification tools and will work closely with the chip architects and RTL / VLSI design teams.
RESPONSIBILITIES
The Verification Engineer will be responsible for different HW blocks at module-level and sub-system level and is expected to:
Have an expert-level understanding of assigned HW blocks as well as a good understanding of the block in the context of whole system.
Communicate with architect, designer, algorithm and other verification engineers to lead complex verification tasks, both on module-level and sub-system testing.
Design complete verification environments.
Implement design in full UVM environment.
Perform full block regressions and collection of functional coverage.

Required Back End Engineer
Working with an ASIC design team, you will participate in the development of next generation SoCs for 5G and 4G wireless network.
You will be responsible for the physical implementation of the chip, from synthesis netlist to GDSII, for power and area optimized chips in advanced nodes (12 nm, 22 nm).
You will also be responsible for the physical verification of the chip.

Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. AWS provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. As part of our Web Services, we are looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

Looking for exceptional senior engineers to join the top-tier team that is developing the next generation semiconductor platform, based on a revolutionary architecture. Engineers will participate in design and verification activities, working on the next generation of our products.

You are invited to take part in developing, integrating and deploying cutting-edge technologies, starting with identification and definition of project requirements, architecture, feature development, and collaboration with the different groups.
Your design will be integrated into the nitro SoC, on millions of servers worldwide. This is an opportunity to have a large-scale impact.
As a VLSI engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities:
*Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.

We are looking to hire a talented VLSI Physical Design engineer to join our VLSI group in Tel Aviv.
You will work alongside other talented engineers to develop our cutting-edge AI chips.
As part of our team you will be involved in all phases of physical design activities and you will take part in developing our special BE flows that enable us to tape out our technology-leading chips.
Responsibilities:
As part of our team, you will be involved in all phases of physical design activities, and you will take part in developing our special BE flows.

We are looking to hire a talented VLSI Design Engineer to join our VLSI group in Tel Aviv.
You will work alongside other talented engineers to develop our cutting-edge AI chips.
If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities:
Bring architecture requirements of our AI Chips to power and area-efficient VLSI implementation with the right performance.
Work along with verification to enable a fully functional design.
Work along with the backend and DFT to converge the design into silicon.
Join the bring-up of the features with SW when silicon is back in the lab and the magic happens.

We are looking for talented and experienced Chip Design Verification Engineers to join our Networking R&D team, developing the industry's most complex communication devices, delivering the highest throughput at lowest power and lowest latency.
Responsibilities:
Definition, architecture, and development of IP-based block-level verification environments in SystemVerilog, integrated and reused in full-chip environments.
Building reference models, verification and simulation of SOC modules according to specifications, including performance calculations.
Working in a combined design and verification team which develops the SOC silicon core units.
Working closely with multiple teams within the organization, such as Architecture, Software, and Hardware.

Design and implement RTL in System Verilog, based on deep understanding of customer requirements, DUT functionality, and system architecture.
Test and debug your designs in simulation and on hardware-based platforms, to reach cloud-scale quality.
Work with software teams on development of drivers and applications.
Deliver the product into cloud production environments and support it through its lifetime.

We are seeking best-in-class ASIC Design Engineers to design and implement the worlds leading CPU's and SoC's. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We are a learning machine that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

We are building a new group in Israel, this group will deliver security engines and risc-V processor IPs to all of our product lines working with all our groups around the world. We are looking for inquisitive, motivated engineers with experience to build this group from the ground up. As a senior member of our design team, you will be responsible for the design and implementation of high-performance, low-power security engines and risc-V processor modules. You will work closely with architects, design engineers, verification engineers, and physical design engineers to accomplish your tasks.

What you will be doing:
Participate in micro-architecture development and document specifications.

Implement in RTL and/or work on the verification team to ensure that the design is functional.

Apply logic design skills to optimize and meet performance and power goals.

Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable and physically implementable design.

We are looking for an experienced, highly motivated software engineer to join our Chip Design Technologies team. As a member of this team, you will be exposed to the world of EDA software development. This field merges electrical and software engineering to create software tools and solutions used to expedite the design and validation of the next generation of product designs. In our company, these products are aimed at advanced data centers, and power AI revolution across the world.

What you'll be doing:

Leading the charge in developing software tools and solutions, crucial for creating cutting-edge design validation methodologies for us.

Enhancing and refining our suite of in-house tools, used in design validation flow.

Collaborating with designers, verification specialists to ensure your solutions seamlessly integrate into our design validation process.

With the slowdown in Moore's law, silicon power management and hardware power optimizations become a critical part of the development of silicon ASICs. We are positioning you for a key role to take on this challenge and become part of our team, so we can continue developing the best devices in the industry!

Our network horizontal power group is seeking for a highly-skilled, physical design engineer to explore, define and assimilate methods for optimizing our products' power with respect to performance and cost. In your role you'll be responsible to develop methodologies, improve tools and flows, driving power optimization and examine silicon power & performance. We are searching for a hard-working, highly motivated, engineer which has both excellent technical skills as well as outstanding personal skills.

What you will be doing:

Establish estimation and optimization techniques for RTL design and physical design teams.

Improve estimation quality and pre2post correlation.

Develop methodologies and flows across the organization for both pre and post-silicon analysis.

Improve RTL to gate level power aware flows and automation.

lead power execution teams with working methods and power model for various product lines.