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Location: Ra'anana
Job Type: Full Time
We are seeking an exceptional and highly experienced Senior System Engineer to join our elite HW R&D team. This role is suited for a seasoned professional (15+ years of experience) in the networking and telecommunications industry, with a proven track record in multi-platform system architecture, hardware/software integration, and deep protocol-level understanding. The ideal candidate will lead and define end-to-end system behavior across multiple layers, ensuring alignment between hardware platforms and software stacks.
You will work closely with internal and external stakeholders to define detailed system specifications, drive platform validation, and ensure our solutions are reliable, efficient, and meet the demanding requirements of service providers.
Key Responsibilities
System Architecture & Design
Own the end-to-end system architecture across various company platforms (routing, switching, timing, and synchronization platforms).
Define and maintain system-level functional specifications and engineering requirements documents (ERDs), covering HW-SW interfaces, thermal, mechanical, power, and performance constraints.
Evaluate and drive platform-level trade-offs (e.g., performance vs. power, scalability vs. complexity).
Collaborate with hardware design, software architecture, thermal, and mechanical teams to ensure cohesive system integration.
CPU selection, boot methodologies, FW upgrades, IC programming, etc.
Technical Leadership
Act as the technical authority on system behavior, network feature interaction, and platform compatibility across various ASIC vendors.
Drive design reviews, providing critical input on system-level implications and interactions.
Detailed Specifications & Documentation
Develop comprehensive and structured documentation: platform requirement specs, interface control documents (ICDs), test coverage matrices, thermal analysis reports, power budgets, and system bring-up guides.
Create and maintain clear, accurate, and implementation-ready specifications to be used by hardware, software, validation, and operations teams.
Thermal, Power & Mechanical Integration
Analyze and approve cooling methods and thermal design requirements (airflow, heat sinks, thermal interface materials, etc.).
Analyze power distribution planning, and integration with PSU/voltage regulator designs.
Work closely with mechanical engineering.
Requirements:
15+ years of experience in the networking/telecom industry, in roles spanning system engineering, hardware-software co-design, platform architecture, and test strategy.
Proven track record of delivering carrier-grade networking systems or data center-scale platforms.
Deep technical expertise in Ethernet switching, IP routing, timing/synchronization, high-speed interconnects, and network processor architectures.
Strong background in thermal/power/EMI/ESD/EMC requirements for telecom hardware.
Fluent in writing clear, structured, and highly detailed technical documents (e.g., platform specifications, RFPs, ICDs, user guides).
Familiarity with compliance standards and regulatory certifications (NEBS, RoHS, CE, etc.).
Excellent verbal and written communication skills - able to work cross-functionally and influence across teams and disciplines.
Familiar with the following concept/Basic Knowledge
SI/PI, HSIO, and LSIO Expertise
Serve as the go-to authority for Signal Integrity (SI) and Power Integrity (PI) across all platform designs:
Review pre-layout and post-layout simulations using SI/PI tools.
Provide technical guidance on High-Speed IO (HSIO) interfaces including:
SerDes, PCIe, 1G//100G/400G/800G/1600G Ethernet, and high-speed backplane interfaces.
Specify Low-Speed IO (LSIO) interfaces such as I2C, SPI, UART, and GPIO, ensuring robust control-plane integration and manageability.
Nice to Have
Testing & Validation Strategy
Define system-level test plans, platform qualification strategies, and test automation coverage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8827954
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Location: Herzliya
Job Type: Full Time
We are seeking talented, creative and disciplined engineers to join the best-in-class team that plays a significant part in the development of new silicon for our eco-systems by engaging in a dynamic, highly collaborative environment with the focus on the following goals.

Deep understanding of components/modules within wireless communication systems and the corresponding calibration and impairment reduction techniques - Develop methods/algorithms to alleviate hardware induced impairments by calibration, cancellation and other applicable techniques - PHY firmware architecture and design, including calibrations, real-time processing flows, collaboration with RF hardware, microcode, and MAC layer.

Develop highly efficient designs delivering outstanding performance, optimizing power and memory footprints while meeting hard-realtime latency requirements.

Debug real-time systems with limited visibility, working hands-on with development boards and lab equipment.

Collaborate with Radio, MAC, and Systems engineering teams to architect, define and implement innovative algorithms, calibrations, and protocols.

Support pre-silicon validation efforts, including simulation, emulation, and FPGA prototyping.

Develop SoC test and calibration capabilities for chip, module, and product factories.

Support post-silicon bringup, validation, performance characterization, system integration and debugging. - Repeatedly measure and optimize results using various test harnesses - Automate calibration and verification processes.
Requirements:
Minimum Qualifications
B.Sc. with 3 plus years of industry experience.
Hands-on experience and working knowledge of wireless systems and protocols such as LTE/NR/WiFi/Bluetooth.
Excellent problem-solving skills to address technical issues during design, development and maintenance phases.
Strong embedded SW fundamentals, including knowledge of design and development-flows, real-time constraints, concurrency, multi-processor systems, caching and virtual memory.
Deep understanding of data structures, object-oriented design, and system architecture in an embedded environment.
Strong software engineering skills including design, development (using C, C++), scripting (Python), and debugging.
Familiarity with low-level hardware interfaces, register and interrupt programming, bare-metal software development, clock and power management.
Experience with configuration (GIT, Perforce) and release management, continuous integration, unit and regression testing.

Preferred Qualifications
Strong understanding of design strategies for maintainability, scalability, and code reuse.
Excellent communication skills, both written and oral.
Highly organized, motivated and passionate about driving results.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8835567
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Location: Tel Aviv-Yafo
Job Type: Full Time
Required Integration Engineer
Job Description:
Join our multidisciplinary integration team and take part in the development and validation of advanced RF-based systems. The role involves hands-on work with complex hardware and software systems, prototype setup and testing, troubleshooting, and close collaboration with multiple R&D teams.
Responsibilities include:
Integration and testing of complex multi-module systems
Involvement throughout the full development lifecycle of RF and digital systems
Setup and validation of prototype systems at both hardware and software levels
Identifying hardware/software issues and driving technical solutions
Working closely with software, hardware, and final testing teams
Participating in challenging, development-oriented projects with strong growth opportunities.
Requirements:
B.Sc. or Practical Engineering degree in Electronics Engineering - mandatory
Familiarity with basic RF concepts - mandatory
Previous experience testing and operating RF-based hardware/software systems - significant advantage
Experience working with lab equipment such as Spectrum Analyzers and Signal Generators - advantage
Good English skills, including conversational ability - mandatory
Spanish speaking ability - advantage
Familiarity with MATLAB - advantage
Background in technological military units - advantage
Excellent interpersonal and communication skills
Availability for full-time work and additional hours when needed
Active civilian security clearance (Secret level or above) - advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8863797
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SOC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with reasoning synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power and design techniques.
Experience in reasoning design and debug with Design Verification (DV).
Preferred qualifications:
Experience with a scripting language like Python or Perl.
Experience with design sign-off and quality tools (e.g., Lint, clock domain crossing (CDC), etc.).
Knowledge of System on a chip (SOC) architecture and assertion-based formal verification.
Knowledge of design techniques.
Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate SDRAM (DDR), Advanced Extensible Interface (AXI), ARM processors.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843747
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design Engineer, Edge AI, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
3 years of experience with RTL development for ASIC subsystems using Verilog.
Experience with speed interfaces such as PCIe, InfiniBand, and their low latency, security, and reliability principles.
Experience with micro architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience with scripting languages (e.g., Python or Perl).
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
Knowledge of FPGA, emulation platforms, and SoC architecture.
Knowledge of assertion-based formal verification.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8843190
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5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
Were looking for a talented Embedded SW Engineer to join our innovative team. As a member of our team, you will be responsible to innovate, design and implement embedded software in C/C++ for our chipset.
Responsibilities:
Design, implement and optimize the embedded software driving our chipset (drivers, middleware and application layer)
Collaborate with System architecture and Hardware groups to deliver quality system solutions
Optimize code for memory usage, performance, and power efficiency
Ensure compliance with Safety and Industry standards.
Requirements:
B.Sc. in Computer Engineering / Electrical Engineering / Computer Science
5+ years of experience in embedded software development on RTOS / bare-metal
Strong C/C++ programming skills
Experience with HW/SW interface development and debug
Self driven, fast learner, ability to work independently and drive tasks end to end
System-level thinking: ability to structure, design, and document maintainable systems
Comfortable working in a fast & dynamic environment
Team player, strong communication skills
Preferred Qualifications
Experience with Automotive certification processes
Experience with Linux development
Experience with Logic / protocol analyzers usage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8863743
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30/09/2026
Location: Petah Tikva
Job Type: Full Time
The ideal candidate will possess strong problem-solving abilities and passion for developing innovative embedded solutions.

In this role, you will design, implement and maintain real-time embedded software for our next-generation wireless power products.

You will report directly to the VP of R&D.

Job Responsibilities:
Design, develop, improve, and maintain real-time embedded software from concept through production.
Define and implement firm architecture on ARM Cortex-M & STM8 microcontrollers.
Integrate real-time embedded software with external hardware components and complete system products.
Collaborate closely with hardware, systems and QA teams to ensure seamless integration and performance.
Participate in code reviews, debugging and system validation processes.
Create and maintain clear technical documentation for design and code.
Requirements:
Job Requirements:
Bachelors degree in Computer Science, Electrical Engineering or Computer Engineering - Must.
Minimum 3 years of hands-on experience in microcontroller programming (ARM Cortex-M series) - Must.
Proven experience in real-time embedded systems design and low-level hardware interfaces (SPI, I2C, UART, CAN, etc).
Strong understanding of MCU architecture and system peripherals (ADC, DMA, PWM, TIMERS, GPIOs, System Clocks, etc.).
Deep knowledge in C programming - Must.
Familiarity with Python and MATLAB - Must.
Solid understanding of the software development lifecycle, including coding standards, debugging, version control and documentation practices.
Proficiency in using lab and test equipment (oscilloscope, logic analyzer, power supplies) - Must.
Excellent interpersonal skills: team player, independent, fast learner, hardworking and reliable - Must.
Strong communication skills in both Hebrew and English - written and verbal.


Advantages:
Experience in hardware design and power electronics.
Basic knowledge of object-oriented concepts in C or C++.
Familiarity with automotive industry standards such as MISRA-C:2004.
Experience with IAR and/or Keil Embedded Workbench development environments.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8838347
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תודה על שיתוף הפעולה
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required ML Hardware Achitect
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will help shape the future of Clouds next-generation AI infrastructure, architecting high-performance Machine Learning silicon designed to power hyperscale AI inference. You will have an opportunity to drive accelerator technology that powers Generative AI models, large language models (LLMs), and emerging agentic workloads where throughput, latency, memory bandwidth, and energy efficiency are mission-critical.
You will be part of a silicon architecture team pushing the boundaries of custom computing. Leveraging your deep expertise in hardware-software co-design, machine learning algorithms, and computer architecture, you will define and optimize custom compute engines and memory hierarchies that accelerate the world's most advanced AI models across Cloud datacenters.
Responsibilities
Lead the architectural definition, modeling, and specification of next-generation, high-performance ML compute IP and acceleration blocks for Cloud AI silicon.
Own the ML IP architecture specification throughout the entire product lifecycle: concept exploration, cycle-accurate modeling, implementation, silicon bring-up, and production.
Partner closely with leading AI research and algorithm teams (e.g., Google DeepMind, Gemini research teams) and software compiler teams (XLA, PyTorch) to explore architectural trade-offs and define hardware requirements for emerging model architectures.
Drive comprehensive architecture studies, evaluating compute dataflows, numerical formats, sparsity, and specialized acceleration mechanisms such as key-value (KV) cache optimization.
Drive performance, latency, power efficiency, and silicon area projections across model topologies and workload configurations.
Requirements:
Minimum qualifications:
Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
15 years of experience in computer architecture, ML accelerator design, or high-performance processor architecture.
Experience leading architectural definition and authoring architecture specifications for silicon or compute IP blocks.
Experience with performance modeling, workload profiling, and hardware-software co-design.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture or ML hardware systems.
5 years of experience leading the architectural definition and microarchitecture of AI/ML accelerators from concept through production.
Deep knowledge of modern deep learning workloads (Transformers, MoE, Diffusion, Generative AI inference) and their system bottlenecks (memory capacity, KV cache bandwidth, interconnect scaling).
Strong understanding of high-performance memory subsystems (custom SRAM architectures, high-bandwidth memory hierarchies, caching schemes).
Experience working with modern ML frameworks (PyTorch, JAX, TensorFlow) and ML compilers/runtimes (XLA, TVM, Triton).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8843260
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Giv'atayim
Job Type: Full Time
We are looking for a talented and experienced engineer to take part in the Emulation and Prototyping efforts for the companys core product. This position involves building a complex emulation environment from scratch, and collaborating with software, design, and verification teams. In this role, you will be leading emulation from A to Z and will have a critical impact on the company.

Responsibilities
Develop and build complex emulation models for coming generations of our accelerators, including transactors like PCIe, SPI, and embedded CPUs.
Work with the software, design, development, and verification teams to understand the functional and performance goals of the products design.
Optimize the model for speed and capacity and develop debug abilities to support software and firmware teams.
Work with software design and development teams to define and develop BFM, test bench, and checker tools.
Review specifications and develop attributes, tests, and coverage plans for the emulation system.
Requirements:
B.Sc. or higher degree in Electrical Engineering from a leading institution.
3+ years experience in building emulation models, running tests on emulation machines, and debugging issues within the time constrictions of silicon design projects while handling multiple priorities.
Experience with emulation platforms such as Palladium, Veloce, or Zebu, including compilation, debug, power, performance, and throughput tuning.
Familiarity with Linux environments.
Experience with languages such as : C, C++, Perl, Ruby, System Verilog, Verilog, Make.
Familiarity with interfaces such as PCIe, SPI, UART, ETH: advantage.
Familiarity with embedded systems: advantage.
Knowledge of FPGA: advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8828221
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תודה על שיתוף הפעולה
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28/09/2026
Job Type: Full Time
We are seeking best-in-class ASIC Design Engineers to design and implement the worlds leading CPU's and SoC's. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We are a learning machine that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

We are building a new group in Israel, this group will deliver security engines and risc-V processor IPs to all of our product lines working with all our groups around the world. We are looking for an Architect with a security experience to help lead the Arch work on security engines and secure boot flows. You will work closely with our security architects, design engineers, verification engineers, and SW engineers to accomplish your tasks.

What you will be doing:

Participate in Architecture development and document specifications.

Work with RTL and the verification team to ensure that the design meets the spec.

Help deliver a design that meets the high security standards of us and our customers.
Requirements:
What we need to see:

A BSc and/or MSc from a major university in electrical engineering or computer engineering.

At least 10 years of relevant experience in ASIC design, uArch and Arch in the areas of crypto engines and root of trust.

A good system level understanding and experience working with multiple groups including ASIC design, FW and SW.

Good interpersonal skills. And team player.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8836044
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a highly experienced Architecture Prototyping Engineer to join our R&D team and turn early-stage architectural concepts into working proof by creating or modifying any or many layers in a system (HW to Cloud).
You'll run bring-up on boards, set up lab benches, write FPGA RTL or embedded code, run simulations, and script measurement setups to take measurements and benchmarks.
You'll work across every electronics discipline, alongside algo, architects, logic designers, RF engineers, embedded developers, and physicists.
What You'll Do:
Build, bring up, and debug hardware prototype boards across analog, RF, power, digital, and mixed-signal domains.
Implement algorithms, write and simulate RTL, or embedded/Linux code
Lab measurements and benchmarks (scope, spectrum analyzer, network analyzer, power analysis)
Work directly with product and system architects to translate an early concept into a concrete, testable prototype.
Document findings.
Requirements:
BSc in Electrical Engineering. MSc or PhD - an advantage.
Proven, hands-on experience in at least one of the following, at real depth: FPGA, digital, analog, power, Python, C/C++, embedded systems, or Linux-based systems.
Ability to quickly pick up and apply a new discipline outside your core expertise (this role is built around that).
Strong lab skills: comfortable bringing up a board, debugging with standard lab equipment, and diagnosing problems that span hardware and software.
Ability to work in a multidisciplinary environment - communicating and collaborating fluently with engineers whose specialty is not your own.
Advantages:
System design and system integration experience.
Multi-disciplinary development or integration.
Experience to more than one of the disciplines above.
FPGA SoC development.
Scripting/automation experience (Python) for measurement or test setups.
This position is open to all candidates.
 
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24/09/2026
Location: Haifa
Job Type: Full Time
We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation.
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.
Requirements:
Required Qualifications
BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
5+ years of engineering experience in silicon validation, post-silicon debug, or high-speed interface development.
Strong hands-on knowledge of PCIe architecture and protocol.
Experience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements.
Strong problem-solving skills and ability to independently drive issues to root cause.
Experience working across hardware, firmware, and software boundaries.
Good scripting/programming skills, preferably Python.
Good Linux knowledge and experience with Linux PCIe debug tools.
Strong communication and collaboration skills.

Preferred Qualifications
Experience with PCIe Gen4/Gen5/Gen6/Gen7
Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity.
Experience with PCIe compliance and interoperability testing.
Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures.
Experience with PCIe switches, or networking/accelerator platforms.
Practical experience using AI/ML tools for engineering debug and automation.
This position is open to all candidates.
 
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8832109
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Micro-Architect, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Lead Design Activities at IPs, SubSystems(S.S) and SoC.
Define the block-level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up, as well as test plan development and coverage analysis for block and SOC-level verification.
Communicate and collaborate with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
8 years of experience architecting networking ASICs from specification to production or equivalent experience.
4 years of experience in technical leadership.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Experience in micro-architecture, RTL Design, verification, design quality checks, physical design aspects of RTL coding, and power.

Preferred qualifications:
Experience architecting networking switches, end points, and hardware offloads.
Experience working with design networking: RDMA or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience working with software teams optimizing the hardware/software interface.
Proficiency in a procedural programming language (e.g., C++, Python, Go).
Knowledge of TCP, IP, Ethernet, PCIE and DRAM.
Familiarity with Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).
This position is open to all candidates.
 
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5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a hands-on FPGA Design Engineer, specialized in high-performance digital design and FPGA-based system development, as part of the QM-Platform team.
This role involves ownership of FPGA interfaces and connectivity logic, including high-speed communication blocks, platform integration, and close collaboration with embedded and hardware teams. You will work on complex FPGA/SoC platforms, enabling robust and scalable solutions for quantum control systems.
Responsibilities:
Own the design and implementation of FPGA-based interfaces such as PCIe, I2C, SPI, and high-speed GT communication.
Develop and integrate FPGA logic on advanced platforms, including Xilinx UltraScale+ and Versal.
Collaborate closely with embedded, hardware, and system teams to ensure seamless HW/SW/FPGA integration.
Drive FPGA bring-up, debugging, and validation at both lab and system levels.
Participate in system architecture definition and cross-team design decisions.
Requirements:
Must-Haves
3+ years of experience in FPGA design and digital system development.
Strong proficiency in Verilog/SystemVerilog RTL design.
Hands-on experience with Xilinx FPGA families (UltraScale+, Zynq, or Versal).
Experience implementing and debugging high-speed interfaces (PCIe, Ethernet, JESD, or similar).
Solid understanding of FPGA development flows, including synthesis, place & route, and timing closure.
Experience with lab debugging tools (e.g., ILA/ChipScope, oscilloscopes, logic analyzers).
Experience with simulation and verification methodologies (RTL and gate-level).
Strong problem-solving skills and attention to detail.
B.Sc. or higher in Electrical Engineering, Computer Engineering, or equivalent.
Strong communication skills and ability to collaborate across teams.
Advantages:
Experience with Versal architecture, including NoC design and integration.
Background in ASIC design or verification.
Familiarity with FPGA backend flows and static timing analysis (STA).
Scripting experience (Python, TCL, Makefile) and/or C/C++ knowledge.
This position is open to all candidates.
 
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28/09/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are now looking for a Senior Chip Design Verification Engineer for the Switch Silicon group.

As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:
Work in a combined design and verification team which develops some of the switch silicon core units.
Build reference models, verify and simulate chip blocks/entities according to specifications.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.
Requirements:
What we need to see:
5+ years of experience in RTL design or RTL verification.
Previous experience in networking - an advantage.
B.Sc. in Electrical Engineering or Computer Engineering.
A team player with good communication and interpersonal skills.
This position is open to all candidates.
 
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