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About our company As a global semiconductor leader, our company  builds the hardware trust foundations powering modern computing - from trusted platform module (TPM) chips safeguarding millions of personal computers to complex root-of-trust architectures across cloud platforms and servers. Security is Embedded into the core of everything we design. As the global regulatory and threat landscape evolves, ensuring our products meet rigorous, gold-standard cybersecurity compliance and certifications is central to our mission and customer trust. About the Role We are looking for a highly motivated Security Certifications & Compliance Engineer to join our team and play a key role in ensuring our products meet the highest security, compliance, and certification standards. This position combines technical security expertise, compliance activities, product security governance, and collaboration with development teams to support industry-leading security products.
What You'll Do Certifications: Lead and support security certification activities, including Common Criteria (CC), FIPS 140-3, CSPN, OCP SAFE, and additional certification programs. Compliance & Frameworks: Support compliance initiatives related to the Cyber Resilience Act (CRA), Secure Development Lifecycle (SDL), NIST SSDF, and customer cybersecurity requirements. Cross-Functional Teamwork: Work closely with engineering teams, management, customers, certification bodies, and security experts across the organization. External Collaboration: Work closely with external laboratories and certification authorities throughout certification processes. Security Readiness: Review development processes, project documentation, and deliverables to ensure compliance and security readiness. Risk & Threat Assessment: Participate in threat modeling, risk assessments, security reviews, and secure development activities. Audits & Standards: Prepare for and support internal audits, external audits, and customer security assessments. Development Security system (DSS): Maintain, improve, and drive periodic activities for the Corporate Development Security system, including supporting security infrastructure, defining asset classifications, and driving employee awareness initiatives. Documentation: Prepare, review, and maintain certification documentation, including Security Targets, Security Policies, certification reports, and lifecycle evidence.

Required CPU Design for Test Engineer, Cloud
About the job
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
In this role, you will be part of a varied team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design-for-Test (DFT) Engineer, you will play a crucial role in DFT design, and support devices of extreme complexity to production. You will be responsible for developing flows, automation, and methodology, executing DFT activities. You will be responsible for test vectors end-to-end, from generating DFT content on complex design, debugging to coverage goals, simulating it at gate level, sign-off DFT to tapeout, and debugging Si results.
Responsibilities:
Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for array DFT, hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvements.
Perform DFT verification at RTL and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT design requirements are met and mutual dependencies are managed.

Were looking a System Test Automation Engineer to drive system-level (HW+SW) verification for our products.

As a System Test Automation Engineer, youll architect and implement automation that exercises complex, integrated systems, not just software layers. Youll design tools and frameworks that interact with real hardware, real sensors, and real signals.

Key Responsibilities
Design and build automation frameworks for testing multidisciplinary systems including RF, sensors, and embedded hardware
Develop test scripts that connect to real hardware through various interfaces (serial, Ethernet, GPIO, APIs)
Perform both manual and automated testing, developing test plans based on real-world use cases and edge conditions
Debug hardware and software issues
Build internal testing tools (log analyzers, simulators, etc.) and create reusable testing components for data capture, validation, etc.

Required HW Architect team leader
About the Group
We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
our Impact:
As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.
What Youll Be Doing:
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence.

Required Design Team Manager, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

Design high-performance analog and mixed-signal ICs optimized for precision, power, and area, driving prototype and product iterations from architecture to silicon validation.

Responsibilities
Design and simulate analog and RF integrated circuits, including critical blocks such as amplifiers, mixers, PLLs, ADCs, DACs, and bias/reference circuits, with a focus on signal integrity, linearity, and precision.

Optimize circuits for power, area, and performance trade-offs, ensuring designs meet system-level requirements across process, voltage, and temperature (PVT) variations.

Collaborate closely with optics, simulation and PCB teams to define architecture and block-level specifications for successive prototypes and product iterations, ensuring tight alignment with overall performance and integration goals.

Work with layout engineers to guide floor-planning and physical design, minimizing parasitic effects and preserving analog precision in layout-sensitive blocks.

Support post-silicon validation and bring-up, defining test plans, analyzing lab measurements, and correlating results with simulation to refine future design iterations.

Language: English at a proficient level. French is a plus.

we are seeking a System Engineer for Precision Tracking to join its R&D team. This role is suited for an experienced engineer with a strong system-level perspective, combining technical leadership, multidisciplinary coordination, and active involvement in the development of advanced tracking systems.
Responsibilites
Overall responsibility for precision tracking technical project management at R&D including planning and monitoring of all R&D activities, planning and monitoring of project R&D budget (material and hours), lead of technical activities with the customer including design reviews, acceptance testing and system assimilation.
Overall responsibility of the system level architecture of complex systems.
Overall responsibility for System, Software and Hardware level specifications and requirements.
Overall responsibility and active participation in the Integration and Proof of Design phases.
Overall responsibility for electrical connectivity design between LR.

Required C++ Software Engineer - Compilers Team
About the team
We are the world leader in automotive and driving assistance systems, developing the world's most advanced software technologies and hardware architectures.
We are providing an end-to-end software solution for development and deploying features on its HW chip - EyeQ.
The compilers team is looking for a C++ Software engineer with a passion for low level optimizations and code analysis.
What will your job look like?
Develop and extend a compiler based on the LLVM infrastructure to support and optimize our EyeQ hardware.
Implement and improve middle‑end and back‑end compiler optimizations.
Analyze generated code to improve performance and efficiency.
Perform real-world benchmark analysis to find optimization opportunities.
Collaborate with chip architects on defining and supporting future hardware generations.

As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities
Execute SoC Top-level physical design and actively drive full-chip convergence.
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff.
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR).
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon.
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration.

We are looking for a Software Engineer to help design and develop the core services and applications that drive our data capabilities. In this role, you will build high-quality, scalable software; contribute to the architecture of our next-generation data systems; and collaborate with research and product teams to turn cutting-edge ideas into production-ready features.
Responsibilities:
Design, develop, and maintain scalable backend services and components that power our data workflows, analytics, and product features.
Build high-quality internal tools and applications that improve engineering workflows and enable data-driven development across the organization.
Contribute to the architecture and evolution of our new data platform with a strong focus on clean design, testability, maintainability, and performance.
Collaborate closely with security researchers, analysts, and product managers to translate innovative cybersecurity concepts into reliable, production-ready software.
Apply engineering best practices across the stack - including code quality, testing, observability, versioning, and documentation - to ensure system robustness as we scale.

We are looking for an excellent Software Engineer to join the network management team. The team develops software responsible for configuring network devices. routing algorithms and performance optimizations in InfiniBand networks powering world top supercomputers. For research and testing purposes, we also develop large-scale InfiniBand network simulators.

What youll be doing:

Design and develop user-space applications responsible for simulation large scale InfiniBand networks of thousands of network devices.

Improve performance and optimize algorithms for using the simulator in Docker and cloud setups.

Collaborate with multiple teams in our multi-functional environment on developing new features/improvements.

Our Imaging Radar group develops innovative high-performance Imaging Radar solutions for ADAS and Autonomous Driving markets. We are looking for a Software Architect to join the development of state-of-the-art products in mmW frequencies.
You will be part of a winning team in a fast-paced startup-like environment, working on many different components of the entire system. You will have an opportunity to make an impact on the design and implementation of an innovative technology in its early stages.
What will your job look like:
Clearly define the requirements. Research the hardware, firmware, and software existing support and define the solution to match the requirements.
Hands-on resolution of complex issues.
Resolve issues raised during implementation stages or feedback from customers.
Develop & communicate high-level designs and technical specifications.
Define responsibilities of system components and interfaces.
Identify risks and propose solutions in system designs.
Define aspects of development; appropriate technology, workflow and standards.
Evaluate existing system designs and propose improvements.
Collaborate with other architects.
Foster innovation through research, recommending the use of new technologies, processes or standards.
Prepare, lead and participate in design reviews.
Take part in all phases of the software development cycle.

Our Analog Layout design team is looking for a Senior Analog Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed mixed-signal circuit designs. We have continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. We are a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our lifes work, to amplify human creativity and intelligence.

What you'll be doing:

Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools.

You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.

Job duties will include floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis.

We are looking for a Staff Engineer to join our Core Engineering group. The group is responsible for the real-time, low-latency infrastructure that powers our fraud decisions and external APIs.
Our systems process billions of requests every day, ensuring high availability, security, and performance at global scale.
In this role, youll work on core backend components such as our decision engine, ingestion and enrichment pipelines, schema management systems, and self-serve API platform. The software you build will power critical business decisions and directly serve some of the worlds largest merchants.
This is a high-impact, high-ownership position for an engineer who thrives on solving complex distributed systems challenges, cares deeply about production-grade quality, and wants to shape the foundation of our decisioning platform.
What you'll be doing:
Design, build, and scale backend systems that power our real-time decisioning and APIs.
Own projects end-to-end - from design and implementation to production rollout and monitoring.
Ensure systems are low-latency, fault-tolerant, and high-throughput across distributed environments.
Enhance observability, reliability, and developer experience through strong operational and tooling practices.
Collaborate with Product, analysts, data scientists, and infrastructure teams to drive innovation across our decision ecosystem.
Participate in technical discussions and customer interactions, providing expertise and clear communication when supporting enterprise integrations.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

Description
- Own critical block and sub-system verification of wireless SoC projects.
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies.
- Define verification plan, create, simulate and debug test scenarios.
- Drive regression and coverage analysis to ensure high quality DV.
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute.