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Were looking for an L2 IT Technician in data center to support and maintain large-scale GPU clusters in a data center environment. We are seeking an experienced IT Hardware Support Engineer to This role focuses on troubleshooting of high-performance server hardware, including GPU clusters.

You will be deeply involved in resolving complex hardware incidents, proactively handling L1/L2 support via the ticketing system. Working closely with IT infrastructure engineers and L3 technicians, you will help optimize diagnostics, reduce resolution times, and continuously improve SLA performance.

This role requires shift work (day & night), that will be compensated.

Your responsibilities will include
Solve hardware related issues with servers, involving in-depth advanced level troubleshooting

Report to hardware problem management, execute workarounds and solutions

Solve proactively L1/L2 tasks through ticket system

Update new processes and documentation for IT hardware team

Collaborate with IT infrastructure engineers and L3 Technicians to improve SLA with complex diagnostics

Improve support processes, documentation and training materials

Basic level of network tasks, troubleshooting and support

As a Performance Software Engineer, you will be instrumental in building the core computation software that runs on custom AI accelerators. Your work will bridge the gap between host systems and proprietary hardware, encompassing everything from a custom on-board kernels to the sophisticated tooling required for real-time debugging. You will be a key player in chip bring-up and the long-term development of high-performance computation primitives and kernels, ensuring our architecture operates with maximum efficiency and deterministic performance.

Responsibilities
Develop and optimize low-level software primitives in C/C++, assembly, and architecture-specific intrinsics, primarily for RISC-V and ARM platforms.

Implement performance-critical kernels, runtime components, hardware abstraction layers, drivers, and firmware operating in bare-metal or highly constrained environments.

Work closely with hardware architects and RTL/design teams to define and validate hardware-software interfaces, memory maps, register interfaces, interrupts, synchronization mechanisms, and boot flows.

Analyze and optimize software for latency, throughput, memory footprint, instruction count, and efficient use of processor and accelerator features.

Bring up and debug software on simulation, emulation, FPGA, and silicon platforms, including low-level hardware/software integration issues.

Develop validation tests, benchmarks, and diagnostic tools for new processor, DSP, accelerator, and SoC functionality.

Contribute to architecture decisions around ISA extensions, compiler intrinsics, memory hierarchy, DMA, cache/coherency behavior, and software-visible hardware features.

Are you passionate about systems programming at the intersection of hardware and software? Do you want your code to directly accelerate the world's largest AI training and inference workloads? The Elastic Fabric Adapter (EFA) Drivers team is looking for Software Development Engineers to design and implement the kernel drivers and userspace libraries that power high-performance networking for AWS's AI/ML and HPC infrastructure.

EFA is the custom network interface that enables thousands of GPUs and accelerators to communicate at near-wire-speed bandwidth and low latency, making it a critical enabler of both foundation model training and real-time inference serving at unprecedented scale. When customers train the next generation of large language models or serve billions of inference requests with tight latency SLAs on our EC2 P5, P6, or Trn instances, it's our driver stack that moves the data.

Key job responsibilities
- Design, develop, and optimize Linux kernel drivers (RDMA/EFA) and userspace provider libraries (rdma-core) that ship to millions of EC2 instances.
- Work directly with custom hardware - collaborate with chip designers to bring new silicon capabilities to life in software.
- Contribute to the upstream Linux kernel RDMA subsystem and rdma-core open-source project.
- Architect solutions for next-generation networking features: GPU-direct RDMA, adaptive routing, collective offloads, and multi-path transport.
- Build monitoring and automation tools to enhance driver testing for functionality, reliability, and performance.
- Own the full lifecycle: from initial hardware bring-up and feature enablement through testing, deployment, and production troubleshooting across the global AWS fleet.

We are looking for a performance modeling engineer to join the team and shape, optimize, and explore our future networking chips and solutions. The role is cross-disciplinary, collaborating with hardware, software, and research teams across the wider company. You will lead workgroups towards technical solutions that will influence the heart of cutting-edge networking products. You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation of networking solutions.

What you'll be doing:
Thoroughly understand our networking solutions across all performance related aspects.
Develop a C++ simulation model to define and evaluate architectural options for our next generation of networking products.
Understand different trade-offs related to solving performance bottlenecks.
Collaborate and lead technical solutions within architecture, uarch, hardware and software teams.
Analyze and model the communication patterns of key DL, GAI, inference, and training applications.
Explore innovative ideas to improve and optimize our chip systems performance.

Required Senior Emulation Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop, execute, and debug full-chip/system on a chip (SoC) tests on emulation platforms.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Define and implement various coverage measures to capture stimulus and corner-case scenarios. Work with software and post-silicon validation teams to reproduce failures on emulation.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out. Explore new verification and emulation methodologies and implement them.

Required RTL Design Technical Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will contribute in all phases of Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Required Senior CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving force behind groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR CAD to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.
You will continuously develop the Electro-Migration and IR Drop (EMIR) flow, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.
Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) flow
Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate closely with Analog/SerDes designers to integrate current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis flow
Understand root-cause analysis for voltage drop violations and EM risks
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data.

we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery Storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. we offer amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. Join our data Centers group and play a key role in developing next generation of innovative, high-performance products. As a Mechanical Design Engineer, you will be responsible for designing electronic packaging solutions from concept to production while collaborating closely with multidisciplinary engineering teams to deliver reliable, manufacturable, and cost-effective products. What will you be doing?
* Design mechanical solutions for electronic products, from concept through mass production.
* Perform PCB mechanical design in close collaboration with Electrical Engineers.
* Design mechanical parts using plastic injection molding, die casting, sheet metal, and extrusion technologies.
* Prepare production documentation, including mechanical drawings, PCB mechanical drawings, and manufacturing files.
* Work closely with cross-functional teams to achieve performance, quality, reliability, schedule, and cost targets.
* Review and approve manufacturing tools, molds, and production specifications.
* Support product validation, first article inspections (FAI), troubleshooting, and design improvements.
* Provide ongoing engineering support throughout the product lifecycle and manufacturing process.
Country:
Israel
City:
Modiin

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Junior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.

Are you looking to be part of a deep-tech team that is shaping the future of global security? Our team does exactly that every single day.

We seek a passionate Robotics Specialist with a Maker mindset and Embedded software-oriented, to join the Embedded team.

Responsibilities - what youll be doing:

Make a major impact on our business goals and take our autonomous initiatives to the next level
Design, develop, and test the embedded software controlling the mechanical aspects of the tractors
Implement the core infrastructure of the conversations between different modules of the systems
Collaborate with multiple teams, customers, vendors, and stakeholders to ensure needs are met
Own the solutions from concept to production and provide excellent support and service to its users

About the Role Our Engineering team leads the bridge between technology, innovation, and design to production. We aim to provide high-quality, professional service by preventing issues in advance and solving them in real-time. We are looking for a hands-on ATE Electronic Engineer with extensive experience in developing electrical cabinets to interface with testing instruments (Bed of Nails, ICT, Spectrum Analyzer). In this role, you will collaborate with Mechanical and Software engineers to define, design, develop, test, debug, and maintain electronic modules for automatic testing systems.
Responsibilities
* Repair of test stations
* Installing new stations in the line
* Perform electronic failure analysis process for company's products
* Determine root cause for failures under investigation and determine corrective actions with the production team

As a Package Engineer, you will work closely with SI, layout, and ASIC design teams to develop complex, top-of-the-line ASIC packages. You will be responsible for planning schedules, resolving costs, packaging, manufacturing, and electrical design issues.

What you will be doing:

Leading development of cutting-edge microelectronics packaging of our Networking Business Units future products, evaluating our products for reliability and performance.

Review manufacturability readiness at each milestone.

Work with world leading vendors to develop highly challenging packaging solutions.

Leading the development of groundbreaking microelectronics packaging for our Networking Business Unit's future products.

Collaborating with world-leading vendors to develop highly ambitious packaging solutions.

Thriving in a dynamic and challenging environment.

Join and lead task forces to investigate and support production excursions, failure analysis and reliability issues and establish quality standards.

Monitor substrate and assembly production KPIs and collaborate with cross functional teams to define and monitor Yield Improvement Plans for continuous improvement and establish quality standards.

Lead process changes reviews, prepare and present data in Change Control Board meetings, lead technical reviews of product changes throughout the supply chain.

we are looking for a Senior Physical Design Engineer.
Your Impact:
You'll be part of the team, which is at the heart of software and ASIC design efforts.
You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.