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be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a SOC physical design engineer, you will collaborate with functional design, design for testing (dft), architecture, and packaging engineers. additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.the ai and infrastructure team is redefining whats possible. we empower customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our  users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
define and drive the implementation of physical design methodologies.
take ownership of one or more physical design partitions or top level.
drive to the closure of timing and power consumption of the design.
contribute to design methodology, libraries, and code review.
define the physical design related rule sets for the functional design engineers.

The Test & Product team is responsible for keeping a target of a very aggressive cost limit of the production testing (wafer sort) while performing comprehensive testing of all the units functionalities. This involves:
Development of the tests using the Teradyne UF tester.
Development of unique and advanced test HW.
Monitoring and analyses the production data.
FA (Failure Analysis) when issues are discovered.
Innovative DFT (design for testability) with the design team.

Responsibilities:
Development of wafer sort test programs through a close relationship with the system team.
Development of the future products DFT and DFM through close collaboration with the design team.
Improvement of the production data analysis and reports through close relationships with the cloud and data teams.
Working with the external abroad test houses.
Decision-making based on massive data analysis (pass criteria, improvements of the tests, identification of failures).
Integrate new and innovative testing methods for a new technology sector.
Specify and work with external vendors for the tester HW (Probe-card and Load-board).
Specify and work with external vendors for the HTOL HW, test program.

We are looking for a seeking an HW Expert to lead feasibility, testing and verification the HW system for the next-generation products. You will be actively supporting new product development throughout the R&D life cycle.
Our goal to lead HW multidisciplinary system implementation. We support and work closely with electrical, optical and mechanical R&D teams throughout development next-generation system.
Responsibilities
What you will be doing:
End-to-end ownership of HW feasibility, integration and qualification activities
Active involvement in new products development throughout R&D process life cycle
Preparation of test plans and reports
Lead new products troubleshooting activities during R&D qualifications, first production tool builds and customer beta evaluations
Technical supervision of suppliers, sub-contractors and external labs
Lead jigs development for R&D, production and service.

Eitan Medical is seeking an experienced Embedded Software Engineer to help develop advanced, reliable, and connected infusion systems. This role is ideal for a hands-on engineer with deep technical expertise who enjoys tackling complex challenges, owning system components end-to-end, and collaborating closely with multidisciplinary teams to deliver high-impact medical devices.
What You’ll Do
* Participate in the full development lifecycle from concept, architecture, and coding to integration, testing, verification, and production validation.
* Design and implement embedded software for safety-critical medical devices.
* Develop firmware, drivers, communication protocols, and RTOS-based components.
* Collaborate with hardware, product, QA, and cloud teams to define and refine system requirements.
* Support board bring-up and perform hardware–software integration and deep system debugging.
* Build robust diagnostics, monitoring, and logging capabilities to enhance field performance.
* Troubleshoot complex issues involving timing, real-time behavior, connectivity, and stability.
* Contribute to architecture discussions, code reviews, and continuous engineering improvements.
* Ensure development aligns with medical-grade quality, safety, and cybersecurity standards.

abra R&D is seeking an Embedded C/C++ Engineer to join the core embedded development team. Join the development of an advanced embedded system used in satellite communication environments, working closely with real hardware, Linux internals, and production?grade OTA/OTI mechanisms. The role focuses on User?Space development in C++ on Embedded Linux, with tight interaction with drivers, kernel behavior and system?level components. Responsibilities
* Develop C++ User?Space applications running on Embedded Linux.
* Apply strong OOP/OOD, modern C++ practices, and smart pointer management to build clean, scalable, maintainable code.
* Perform system integration with Drivers, Kernel components, hardware modules, and other system services.
* Read, understand, and occasionally extend Driver?level C code to integrate user?space logic with low?level operations.
* Work within a true Embedded Linux production environment, including participation in OTA/OTI update flows and fail?safe mechanisms.
* Handle system?level communication and protocols (Basic Networking/IPC).
* Collaborate closely with engineering teams, including a remote team in the UK—professional English is required.

As an Associate Application Engineer, you will be involved in a structured Associate Application Engineer Training Program. This is a fast-track paid training program that challenges you to develop the expertise needed to tackle difficult technical problems.
Associate Application Engineers are members of a team of highly motivated individuals working with customers crafting the most sophisticated hardware and software systems in the world and whose applications span the electronics industry. This training program will give you outstanding insight into our technical marketing, product support, and sales organizations. Upon successful completion of this 12-month training program, you will be eligible to advance into one of these organizations.
The job location is in Israel in our Raanana office.

at our company, we are building the ai factories that power the future of human intelligence! as we scale from thousands to millions of gpus, the "pipes" that connect them have become the most critical bottleneck in modern computing. this is where you come in! we are looking for a visionary senior system architect to lead the charge in defining how we move data at speeds the world has never seen. we want to bridge the gap between silicon and the rack, ensuring our nvlink and infiniband fabrics remain the gold standard for performance. this is a chance to join a team where we don't just follow industry standards-we set them!
you will work at the intersection of signal integrity (si), mechanical engineering, and system protocol design to ensure that our nvlink and infiniband/ethernet fabrics scale to terabit-per-second speeds with industry-leading power efficiency and reliability.
what youll be doing:
architectural definition: lead the end-to-end definition of high-speed interconnect systems for next-gen ai platforms (e.g., rubin and beyond), focusing on 224g/448g pam4 lanes and beyond.
technology roadmap: evaluate and select pioneering technologies such as co-packaged optics ( CPO ), silicon photonics, and advanced osfp/qsfp-dd form factors.
system co-design: collaborate with asic, thermal, and pcb teams to optimize the "silicon-to-connector" path, minimizing insertion loss and improving signal integrity.
standardization leadership: represent our in industry standards bodies (e.g., ieee 802.3, ocp, msa) to influence the future of high-speed connector and cable specifications.
vendor ecosystem: work with world-class connector and cable vendors to drive custom mechanical and electrical designs that meet our unique performance requirements.
performance modeling: conduct trade-off analyses between reach, power, latency, and cost for various interconnect media (copper vs. optical).

nvidia's new product introduction (npi) team is growing, and we're looking for a highly motivated and diligent engineering vendor manager to join us. in this critical role, you'll be responsible for the engineering management of our most strategic and technologically advanced suppliers, ensuring the highest quality and reliability of components for our groundbreaking products.
 
nvidia networking division is a leading supplier of innovative end-to-end nvlink, infiniband and ethernet connectivity solutions and services for servers and Storage. we offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. our products optimize data center performance, using nvidias ai solution and deliver industry-leading bandwidth and scalability. in addition, we serve a wide range of sectors, including high-performance computing, enterprise, data centers, cloud computing, Big Data, and web 2.0.
what you'll be doing:
lead engineering engagement with strategic and critical suppliers for new product introductions (npi) and ongoing production, identify potential risks, critical parameters, and areas for optimization
define and implement clear monitoring and documentation requirements for key process steps to ensure consistency and quality
establish comprehensive quality criteria and outgoing quality control (oqc) procedures at suppliers prior to shipment
monitor and analyze supplier yield data, production metrics, and quality performance to identify trends and drive corrective actions
collaborate closely with internal nvidia engineering teams (design, product, reliability, quality) to ensure supplier capabilities align with product requirements
drive continuous improvement initiatives at suppliers to enhance process control, yield, and overall product quality
conduct supplier technical audits and provide mentorship on standard processes in manufacturing and quality control
act as the primary technical interface between nvidia and strategic suppliers, resolving complex engineering challenges

As a Senior/Staff Design Verification Engineer, you will be a key architect of quality in our Israel R&D center. You won't just run tests-you will design comprehensive verification strategies for high-performance digital blocks, IPs, subsystems, and full-chip integration. You will work at the cutting edge of AI infrastructure connectivity where "good enough" isn't an option, owning end-to-end verification plans for our most challenging designs. If you thrive on solving complex verification challenges and want to ensure the quality of chips powering the world's largest AI clusters, this is your opportunity.

Key Responsibilities

Verification Environment Architecture & Development

Design and develop comprehensive ASIC verification environments across all levels-from unit-level and subsystems to full-chip integration
Build sophisticated SystemVerilog/UVM-based testbenches including protocol/traffic generators, monitors, checkers, and functional coverage models
Own end-to-end verification plans for highly complex digital blocks, defining the "how" and "what" to ensure 100% functional coverage
Quality Assurance & Debug Excellence

Drive the debug process and leverage advanced methodologies to find critical bugs before silicon
Develop and execute comprehensive test plans to verify functionality, performance, and corner cases
Ensure verification closure through rigorous coverage analysis and assertion-based verification
Cross-Functional Collaboration & Technical Leadership

Partner with design and system architects to solve intricate hardware verification challenges
Work alongside world-class teams where knowledge sharing and technical excellence are the standard
Contribute to verification methodology improvements and automation initiatives

We are looking for an experienced hardware-oriented technical writer to join our ranks, mainly for documenting:

3D models of hardware
Installation or deployment procedures
Part replacement and maintenance procedures
Related software procedures

Lead the functional sign-off for complex FPGA designs by architecting scalable, reusable UVM-based verification environments.
You will build the essential infrastructure that empowers FPGA designers to efficiently and accurately verify their own modules.

Key Responsibilities:
* Architecture: Build and maintain advanced simulation environments from scratch using UVM and SystemVerilog.
* Strategy & Coverage: Develop comprehensive verification plans to drive the team toward 100% functional and code coverage closure.
* CI/CD & Automation: Architect robust automated regression testing environments and integrate them into CI/CD pipelines (e.g., Jenkins).
* Tool Expertise: Serve as the internal authority for EDA tools (like Questa) and manage high-performance simulations.
* Debugging: Perform deep root-cause analysis on complex failing tests and hardware logic.

As the Physical Design Chip Top Expert you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SoC Top level for chips that drive the worlds largest AI clusters. As PD Top Level Lead, you will own all PD disciplines of the Chip and own the T.O GDS that meet the chip signoff Criteria (Timing, LVS, EMIR, DRC, PV etc. ) ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

SoC Top level Ownership and oversee the Chip convergence.
Take full ownership of Top Level physical implementation, including floor planning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Work Closely with Package team on Bump map to Ballout taking into consideration all Signal integrity aspects

We are looking for a talented Full stack Engineer with a strong backend and UI orientation and exceptional skills to join our Harmony SASEs forefront team, which building cutting-edge, large-scale solutions that redefine cloud security and network management.
Job Id: 22645
As part of our team, youll work with the latest technologies, solve complex engineering challenges, and play a key role in developing scalable and resilient fullstack systems. If youre passionate about innovation, cloud security, and high-performance architecture, this is your opportunity to make an impact!
We are a key player in the network security field, striving to provide the leading SASE platform in the market. Our innovative approach, merging cloud and on-device protection, redefines how businesses connect in the era of cloud and remote work.
Key Responsibilities
End-to-end features development including research, design, testing, deployment and monitoring
Contribute to technological and architectural decisions
Develop testable, reusable, and effective code to create high performance application
Analyze and improve efficiency, scalability, and stability of various components in our system
Collaborate with Designers, Product Managers, Architects and Software Engineers to deliver the best product to our customers.

we are looking for an Experienced Verification Engineer for an exciting Job in its complex SoC/FPGAs, Networking and Modem verification team.
Performing Verification in the most advanced verification methodologies/tools, implementing State of the Art verification for complex ASIC.
We are looking for talented verification engineer which have abilities to own complex tasks on one hand and on the other hand be a team player, working with different vertical team and disciplines.
What Youll Do as a Part of Your Role:
Responsible for the Verification of Various IPs and top level designs.
Defining and implementing the Environment architecture from scratch.
Defining and implementing Test plans, coverage plans, etc.

Were looking for a highly motivated and experienced automation engineer with a strong passion for quality and performance.
Job Id: 24550
If youre passionate about quality and efficiency, then join our team. You will play an important part in Harmony SASEs product development process. You will create and implement strategy for quality coordination and automation testing, as well as suggesting solutions to identified quality problems.
You will also be responsible for designing, developing, and executing performance testing strategies for our cybersecurity solutions to ensure optimal performance and scalability. You will collaborate with development teams to identify performance requirements for new features and releases, and work with them to ensure that performance issues are addressed before they impact our customers. The successful candidate will have a strong technical automation background, experience with performance testing tools and methodologies, and a passion for delivering high-quality software. If you're a self-starter who is eager to learn and take on new challenges, we encourage you to apply.
Key Responsibilities
Create and maintain automation frameworks for the R&D products
Design, automate and implement test cases for a variety of products, using the latest technologies on the market
Develop and apply integrated testing processes for new and existing products, using the latest tools and technology
Review requirements, specifications, and technical design documents to provide timely and meaningful feedback
Use different testing techniques and test-driven development strategies
Work hand-in-hand with manual QA to learn about the system and find ways to improve the automation flows
Creating testing tools to improve our QA capabilities
Build load and performance testing frameworks
Identify key KPIs for product quality
Challenge our methodologies and tools and strive to continuously improve
Monitor and analyze performance metrics to proactively identify potential issues
Experience with working and configure monitoring tools such as DataDog Grafana Etc.