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Required Hardware/Electrical Engineering BS/MS Intern, 2027
Please complete your application before November 13, 2026. We encourage you to apply as early as possible as we review applications on a rolling basis.
About the job
The Cloud and AI Infrastructure team in Israel focuses on building our next-generation systems. The team's work is grounded in creating custom hardware, and as an Intern, you'll get to collaborate with engineers from various parts of the organization to influence the future of Cloud and the AI infrastructure by working on the foundational technology that makes it all possible. This is the hardware that powers everything, from Cloud to our most advanced models like Gemini.
As an Electrical Engineering Intern in the domain of Very Large-Scale Integration (VLSI), you will work on designing, developing and verifying next generation chips for our Cloud Compute Infrastructure. You will have the opportunity to collaborate with engineers from various parts of the organisation to help develop our next generation systems on chip (SOC).
Responsibilities:
Responsibilities and detailed projects will be determined based on your educational background, interest and skills.

Careers that change lives start here. we are a global leader in healthcare technology with a Mission to alleviate pain, restore health, and extend life. Our 95,000 employees work across more than 150 countries to put patients first - developing innovative medical technologies that improve the lives of 72+ million patients each year. Your unique talents will help shape the future of healthcare while building a career grounded in purpose, growth, and impact.
A Day in the Life
our company Endoscopy is pioneering the future of medical diagnostics with innovative capsule endoscopy solutions. Imagine a world where diagnosing gastrointestinal conditions is as simple as swallowing a pill which captures with imagers and different sensors the digestive system and transmit it in real time. Our cutting-edge technology not only makes this possible but also revolutionizes the patient experience, providing a non-invasive, accurate, and efficient diagnostic tool.
We are seeking a highly motivated and experienced System Engineer to lead multidisciplinary system engineering activities for innovative medical device products. The role involves driving system architecture, leading feasibility research activities followed by the ownership of requirements definition, technical risk management and cross-functional integration definition throughout the product lifecycle.
The ideal candidate combines strong technical expertise with a systems-thinking mindset and has experience working with complex products involving hardware, firmware, wireless communication and algorithms.
This position will play a key role in both sustaining existing products and developing next-generation technologies from concept through commercialization.
Primary responsibilities:
Lead system architecture, requirements definition. Translate user, clinical, business, and regulatory needs into clear, traceable system requirements and specifications.
Drive cross-functional collaboration across product , marketing , HW, FW, SW, AI and DQA teams.
Own system-level integration and performance evaluation activities throughout product development.
Identify technical risks, perform root-cause investigations and technical trade-off analyses. develop reliable analysis strategies to ensure product quality and reliability.
Support technology innovation, feasibility studies and evaluation of new technologies and system concepts.

Join our company as a DFT Engineer, where you will lead the design for testability (DFT) efforts to ensure optimal manufacturing and quality assurance processes for complex electronic systems.
Responsibilites
Implement DFT methodologies to improve the testability and manufacturability of electronic products and PCB assemblies.
Review schematics and PCB layouts, ensuring compliance with DFT guidelines and recommending improvements for enhanced test coverage.
Collaborate with hardware design teams to integrate DFT solutions during product development.
Perform test coverage analysis using TestWay or similar tools, define test point requirements, identify coverage gaps, and provide recommendations to development teams.
Define and maintain manufacturing test strategies, including ICT, Flying Probe, Functional Testing, and Boundary Scan (JTAG).
Develop, configure, and execute JTAG/Boundary Scan tests and create test programs for validation and production environments.
Lead test pattern generation, validation, and troubleshooting activities to ensure efficient and reliable testing.
Analyze and resolve DFT-related issues throughout development, validation, and production phases.
Define requirements for Automated Test Equipment (ATE) and support the deployment and maintenance of production test systems.
Provide technical leadership and mentorship to engineers while driving continuous improvements in testability and manufacturing processes.

We are seeking a Package Layout Design Engineer to join our hardware team and contribute to the physical design of advanced IC packages for next-generation machine learning and data center ASICs.
In this role, you will execute package layout tasks from floor planning through tape out and manufacturing release, working closely with senior engineers, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet performance, density, and reliability targets.

Key job responsibilities
- Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
- Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
- Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, and decoupling capacitor placement.
- Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates or silicon interposers.
- Support die-level RDL routing and bump planning in coordination with ASIC physical design teams to help co-optimize the die-package interface.
- Contribute to cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels under guidance from senior engineers.
- Assist in maintaining package stack-up definitions in collaboration with SI/PI and materials engineering teams.
- Run physical verification checks (DRC, connectivity, shorts/opens) and support design closure.
- Follow and help refine package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance.
- Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout - impedance-controlled routing, power plane optimization, and critical net shielding.

Required Junior RTL Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design experience to be part of a team that develops complex ASIC System-on-Chip (SoC) intellectual property from proof-of-concept to production. This includes creating IP Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies, including design generation automation. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing, etc. You will develop/define design options for performance, power and area.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog).
Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
Contribute to verification test plan and coverage analysis of block and SoC-level.

Required SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams

Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities

Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration

We are seeking a highly motivated and technically skilled Software and Field Application Engineer to join our team, supporting the integration of our state-of-the-art automotive imaging radar technology into the next generation of vehicles.
Our vision is to bring new and cutting-edge automotive radar sensor solutions, while leveraging our assets and expertise in this field. Introducing best in class Radar sensor that would complement our end-to-end autonomous driving solution platform. You will be joining an excellent group of people, working on a cutting-edge mmWave Radar Technology and enjoy a dynamic and challenging environment.
What will your job look like?
Lead integrations of new features with our System, Software and Algo groups.
Develop tools to help us shine - it can be GUI tools, Simulators, data validity tools etc. - anything needed to help us win.
Work closely and Collaborate with our R&D team to understand customer needs and translate them into technical solutions.
Collaborate with customers throughout the development cycle, from initial concept and feasibility studies to product integration and deployment, including on-site technical support and demonstrations.

Required Senior Emulation Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop, execute, and debug full-chip/system on a chip (SoC) tests on emulation platforms.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Define and implement various coverage measures to capture stimulus and corner-case scenarios. Work with software and post-silicon validation teams to reproduce failures on emulation.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out. Explore new verification and emulation methodologies and implement them.

Required Senior DDR Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing. You will verify digital designs, collaborate closely with colleagues on projects, and perform direct validation. You will construct testbenches that exercise hardware through corner-cases and expose bugs. You will manage the full life-cycle from planning and execution to closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required Senior Edge-AI SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're the driving force behind groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

We are looking for a Systems Engineer to join the Integrated Metrology team, a multidisciplinary group of physicists and engineers working together to implement cutting-edge metrology technologies in the semiconductor industry from a unique and innovative perspective.
The role combines theoretical and experimental system engineering and provides the opportunity to work on advanced multidisciplinary optical measurement products throughout their lifecycle, from customer needs and early development stages through integration, product transfer to manufacturing, and support at customer sites.
Responsibilities
What you will be doing:
Perform theoretical and experimental systems engineering to support state-of-the-art new and existing multidisciplinary optical measurement products.
Drive the full system lifecycle, from understanding customer needs through feasibility and concept evaluation, translating them into cross-disciplinary system requirements, while defining and managing system KPIs.
Conduct laboratory and on-site system diagnostics, troubleshooting, and problem-solving, including root-cause analysis, mitigation plans, implementation of robust system calibration methods, and product transfer to manufacturing.
Work closely with multiple disciplines, including physics, optics, algorithms, mechanics, electronics, and software.
Translate customers high-level requirements into detailed technical specifications.
Support system integration, validation, and product maturity throughout the development lifecycle.
Travel to customer sites worldwide approximately 2-3 times per year.

We are looking for a Senior Software Engineer to provide broad technical leadership for BlueField ARM processor platform boot, from early firmware through Linux login. Do you enjoy looking beyond the problem in front of you and asking how technology, tools, and engineering methods should evolve for the next generation of products? This is an opportunity to have an impact well beyond individual features! We value technical depth, curiosity, and practical innovation, and we want this role to help raise the technical capabilities of the entire organization. This senior individual-contributor position spans firmware, kernel, architecture, and product teams. You will help drive current product development while also shaping future technical direction, introducing new tools and methods, and improving how our teams develop, debug, validate, and understand complex systems.

What you'll be doing:

Own the technical strategy and roadmap for BlueField platform boot integration, from early firmware through Linux login.

Set the technical direction for platform boot integration in partnership with the architecture team, experienced domain experts, product teams, and firmware partners.

Lead the most complex cross-layer technical issues and drive technical decisions with architecture and domain experts on reliability, security, performance, recovery, and platform readiness.

Define the operating model for boot integration: interface contracts, qualification criteria, release decisions, technical risk management, and escalation paths across organizations.

Identify and assess emerging technologies, development methods, and tools. Drive adoption where they improve product capability, quality, engineering efficiency, or time to debug.

Were expanding our teams and looking for an Experienced Physical Design Engineer who is ready to make a massive impact
NOTE: By applying for this position, you will have the opportunity to indicate your preferred work location: Haifa or Petach Tikva.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS .
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).

Required Experienced SoC Verification Engineer
About the team:
Our SOC verification group owns the important and challenging job of verifying our chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.