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Required Staff Design Engineer, Edge AI, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Required Analog Design Engineer
Job Location:
Israel, Hod HaSharon (Hybrid)
Job Brief:
Be part of the team that is responsible for developing and optimizing the state-of-the-art analog circuits that power our embedded ReRAM and mixed-signal products.
Job Description:
In this role, you will take the lead on designing high-performance analog circuits, driving innovation in mixed-signal systems from concept through production. Youll partner closely with digital design, system architecture, and process engineering teams, playing a key role in bringing our next generation of memory products to market:
Design and develop complex analog circuits, including amplifiers, complex memory arrays, and LDOs, ensuring reliability and performance
Collaborate with cross-functional teams to define system specifications and architecture, translating requirements into actionable designs
Conduct thorough simulations and analyses to validate designs, using tools such as Cadence Virtuoso and Siemens Solido while identifying and mitigating risks early in the design process
Oversee the transition of designs from prototype to production, ensuring compliance with quality and industry standards
Apply deep expertise in analog circuit design - including amplifiers, voltage references, comparators, and ADCs/DACs - to push the boundaries of performance.

The Networking Diagnostics team is seeking a highly motivated and experienced engineer. This person must have hands-on technical expertise to develop critical diagnostic tools for our newest, world-leading networking platforms. This position offers the opportunity to have a real impact in a dynamic, technology-focused company, impacting data centers and high-performance computing (HPC) clusters across the world. We are looking for independent engineers who excel in a fast-paced environment and are passionate about ensuring the stability of next-generation hardware.

What you'll be doing:
Design & Implement: Architect and develop high-performance diagnostic tools and frameworks using Python, tailored for our latest networking platforms.
Performance Optimization: Drive end-to-end development focusing on software that performs efficiently, ensuring diagnostic suites can handle high-throughput data and real-time monitoring without latency.
System Diagnostics: Take charge of developing features that bridge the gap between complex hardware behaviors and software-level diagnostics.
Collaborative Problem Solving: Partner with hardware, firmware, and driver teams to address real-world challenges that demand innovative solutions and a customer-centric approach.
Autonomous Execution: Own the full software development lifecycle of diagnostic features, from initial hardware specification to deployment in dynamic environments.

Required SoC Test and Product Engineer Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high volume manufacturing at wafer fabs and outsourced semiconductor assembly and tests (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next generation of chips. You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices.
You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.
Responsibilities
Develop and implement strategies for high-volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, defective parts per million reduction, test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and SLT.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and return merchandise authorization managing.
Drive product leadership for silicon engineering organization from architectural definition to global availability.
Collaborate with cross-functional teams across the globe including ATE and SLT test engineering, quality and reliability, packaging, supplier management and operations to build, deploy, and maintain a high volume manufacturing screening solution.

Required CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing,
Responsibilities:
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and universal verification methodology (UVM), or formally verify designs with SystemVerilog assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

We are seeking a highly experienced professional with a strong background in RF, digital, and system-level testing, and with the ability to guide technical decisions, solve complex integration challenges, and support advanced test equipment for production environments.

What will you do:

Design and develop Automated Test Equipment (ATE) for RF, digital, and mixed-signal products at board and system levels.

Lead the technical definition and implementation of test strategies in collaboration with R&D, product engineering, and manufacturing teams.

Own the technical analysis of system schematics, block diagrams, and interface requirements to define robust and reliable ATE solutions.

Support production lines by troubleshooting test failures and optimizing test processes for yield and throughput improvements.

Provide technical guidance for integration with software and firmware control and automation systems.

Evaluate and select test instruments, fixtures, and measurement techniques based on product specifications.

Maintain documentation for test systems, including design files, calibration procedures, and troubleshooting guides.

Mentor engineers and technicians on ATE methodologies, operation, and maintenance.

We are developing leading edge products, manufactured on leading edge technologies. We offer a dynamic, open, teamwork environment operating at high pace mode.

Key job responsibilities
Primary responsibilities:
- Development of DfX (DfM, DfT, DfQ&R, etc.) methodologies and BKMs (Best Known Methods).
- DfX activities during the product design stage.
- Product quality & reliability validation (QRV) and ongoing quality & reliability monitoring (OQRM).
- Q&R engineering of volume manufacturing: auditing, monitoring, risk assessment and disposition of non-conformance events/non-conforming material, defining and implementing corrective actions.
- RMAs: investigation, disposition, reporting and follow-up.

Required Silicon Test and DFT Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop Automated Test Equipment (ATE) test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high-volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Manage product sustainment support, including analyzing volume data, improving test time and yield, assessing test escapees and return merchandise authorizations (RMAs), localizing failures, implementing containment measures, and partnering with design, manufacturing, and quality and reliability teams to identify root causes and implement corrective actions.
Build tools, flows and methodologies to continuously improve and automate the testing life-cycle.

As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing

Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness

Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

We are looking for an experienced DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting-edge technologies - Autonomous Vehicle (AV) SoC.
We know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
Develop all the necessary HW / FW / SW for the different modules.
Verify and Validate our design.
Debug and analyze coverage and yield loss.
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts - as it required by the Automotive and Safety related products market (ISO26262).

Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS.
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

We are looking for an excellent design engineer to join our team and build QM's state-of-the-art control and orchestration platform. We are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicists
Responsibilities:
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation)
Learning system and SW requirements for proper implementation of HW-SW interface.

We are looking for highly motivated engineers who love the challenges and the opportunity of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.

We are seeking a passionate QA Engineer to join our FW testing team. This position will be part of our growing team, helping NVIDIA products meet industry-leading benchmarks for efficiency and quality. As a Firmware QA Engineer, you will be immersed in the latest advancements and actively contribute to developing world-class products. Your efforts will directly impact the performance and quality of our offerings, ensuring they consistently meet industry-leading standards.


We are looking for ideal candidates who will actively test industry-leading features in the FW sector, quickly learn new features, conduct both manual and automated testing, and contribute to the development of automation systems.


What you'll be doing:
Review arch design and requirements documents for new features introduced in the Nvlink program.
Join the effort of QA shift left towards simulation for NVL7 generation.
Design, develop, and perform tests for the new features, as part of FW GA or update releases.
Automate newly added tests in the existing automation framework, and add new capabilities and features to the framework.
Report bugs found during execution, assist with reproduction and debugs to understand root cause, verify bug fixes provided by R&D team, and raise if not fixed.
Fully collaborate with different external teams like : :product marketing, R&D, and verification.
Define and build setups topologies for appropriate product coverage.

Experienced Machine Learning Engineer
About the team:
Our Hawkeye team is developing advanced close-range 3D perception for autonomous vehicles, enabling safe automated parking and low-speed maneuvers in tight environments. We build multi-camera deep learning systems for precise and reliable understanding of the vehicles surroundings.
What will your job look like:
Research and develop cutting-edge end-to-end 3D perception models combining geometry and semantics.
Work on 3D Semantic Occupancy, Geometry Reasoning, 3D Reconstruction, 3D Object Detection, and related tasks.
Innovate in multi-view fusion, motion handling, and spatial representation learning.
Deliver models that run on real vehicles and integrate into production systems.