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we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

Required Machine Learning Hardware Architect, Hardware, Software Co-Design, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Machine Learning Hardware Architect within the Co-design team, you will serve as a technical lead bridging model architecture innovation and next-generation hardware design. Operating at the highest levels of AI research and engineering, you will define the goal and architectural roadmap for our future machine learning serving and training capabilities. You will guide the integration of ML research such as massive-scale foundation models with advanced silicon architectures to create industry-leading, high-performance, and power-efficient accelerators.
Responsibilities
Define and drive the technical roadmap and architecture for the hardware/software stack to ensure exceptional performance for ML models. Act as the technical liaison across research, software, and hardware teams, steering model architecture innovation to maximize scaling, quality, and hardware efficiency.
Architect next-generation configurable simulation frameworks and performance models, setting the organizational standard for evaluating complex microarchitectural decisions. Drive high-stakes choices regarding Power, Performance, Area (PPA) and buildability for future chip and system architectures, expertly balancing long-term technological trends with strict product delivery timelines.
Guide system-level performance analysis across highly distributed ML systems, innovating new methodologies to optimize and balance compute, memory bandwidth, and inter-chip network requirements. Their leadership will directly shape the future of high-performance AI infrastructure and hardware-software co-design.
Manage cross-functional partnerships across hardware, compiler development and ML teams.

We are looking for talented engineers to help us develop a semiconductor platform based on revolutionary architecture.
Take part in the development of cutting-edge products within a disruptive system architecture. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, within a dynamic, open, fast-paced environment. Our Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world.
We are looking for excellent electrical engineering graduates to join our talented Physical Design team, which develops our next generation products for the cloud market.
We will be conducting a unique training program for three months, where where you will be studying the following with our technical experts and team leaders:
* Backend development flow and stages (RTL to GDS).
* A wide variety of relevant tools and knowledge.
* Practical experience with the most advanced technologies in the industry.

Key job responsibilities
Join our three-month training program where you'll work alongside technical experts and team leaders to gain:
*Backend development expertise (RTL to GDS flow).
*Hands-on experience with industry-leading tools and technologies.
*Practical skills in AI-driven innovations and cutting-edge methodologies.
You'll collaborate with cross-functional teams throughout the chip development cycle and become an essential part of our dynamic physical design team, playing a critical role in next-generation cloud computing solutions development.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.
You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.
Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip
Collaborate closely with Physical Design team to insure a full power integrity
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)
Understand root-cause analysis for voltage drop violations and EM risks.

We're looking for a Design Verification Team Lead - a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Nitro system SoC, the foundation of AWS's virtualization, networking, and storage offload infrastructure.

It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written

It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack, with particular emphasis on networking workloads such as ENA and EFA

It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality

It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development

Key job responsibilities

- Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with a strong connection to networking flows (ENA/EFA).

- Verify IO sub-system features, including interconnect protocols and various accelerator engines.

- Develop and debug C embedded SW as part of hardware-software integration verification.

- Build and maintain UVM-based verification environments for various clusters and sub-systems.

- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.

- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).

- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.

- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.

- Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness.

Come join us and help shape groundbreaking solutions by designing, developing, and testing some of the most complex ASICs in the industry.
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
Handle all chip validation aspects, including:
Building validation plans.
Performing EPSV using advanced test and measurement equipment.
Writing tests in Python over device SDK.
Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.

We are looking for an experienced FPGA Design Engineer who will play a pivotal role in developing , designing and optimizing FPGA solutions for our cutting-edge projects. Your expertise will drive innovation and excellence in digital design as part of the detection team in CT\AMI.

Your role :
Develop FPGA logic using VHDL / Verilog.
Design and implement high-speed data paths and interfaces such as DDR, PCIe, Ethernet.
Perform simulation, verification, timing closure, and debugging.
Integrate FPGA with soft processors (such as MicroBlaze / Nios), sensors, ADCs/DACs, and other system components.
Support system bring-up, lab validation, and debugging at both board and system level.
Collaborate closely with hardware, firmware, software, and system teams.
Support and participate in architecture discussions and design reviews.
Read and understand board schematics to support integration and troubleshooting.
Perform lab and system-level testing after component changes or design updates.
Document FPGA design, interfaces, and implementation details.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Required Senior Silicon DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Required Senior Design Engineer, Edge AI, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, youll work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
Youll be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

*Part-Time or Full-Time Opportunity

Responsibilities:
The research focuses on designing next-generation rack and SuperPod architectures that combine elasticity through resource pooling with optimal performance enabled by holistic co-design across applications, parallel programming models, interconnect fabrics, and compute, memory, and switch chip architectures. On the communication side, the work architects scalable, high-bandwidth, and low-latency scale-up fabrics across multiple chips at rack and SuperPod scale. On the memory side, it explores richer protocol semantics beyond traditional load/store operations to reduce unnecessary data movement and rethinks memory hierarchies to expose large-scale capacity with near-local latency. On the compute side, it analyzes the requirements of General Compute and Generative AI workloads and their parallel programming models to fully leverage large-scale system resources.
Investigate and prototype new architectural features, including but not limited to:
o Tiered Memory: Explore advanced memory organizations, including hardware-managed caching, to enable software-transparent, fine-grained promotion and demotion of cache lines across the memory hierarchy.
o Prefetching/Speculation: Evaluate and design existing and next-generation hardware prefetching and speculation mechanisms to effectively hide local and remote memory latencies at rack and SuperPod scale.
o Near-Memory/Network Processing: Develop support for key primitives executed at the memory and network layers to minimize unnecessary data movement across sparse, dense, and pointer-based data structures.
o Workload-Centric Co-Design: Study optimal parallelization strategies at rack and SuperPod scale for both General Compute and Generative AI workloads, and design dedicated hardware support for widely used parallel programming primitives such as RPCs and collective communication.
Write reports and papers on the research results and present them.

Power the Future with us!  we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery Storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. we offer amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. We are seeking a sharp, experienced Hardware team leader to lead the design of the digital and mixed-signal boards at the heart of advanced energy Storage products. This is a hands-on technical leadership role for an engineer with deep, real-world experience in the disciplines that make or break a mixed-signal design - grounding, EMI, robust communication, and accurate measurement - and, just as importantly, in how these are verified at the board and full- system level. What will you be doing:
* Leading the HW design of the digital and mixed-signal boards and products, from concept through mass production
* Owning the design of accurate measurements, robust communication, grounding, and power distribution - across the boards and at the system level
* Defining how these are verified and characterized, both on the bench and within the complete system
* Managing and growing the team - owning the team's tasks, design reviews, and timelines
* Leading several development projects in parallel, across all project stages up to mass production
* Working in a multidisciplinary environment and collaborating across departments and sites
Country:
Israel
City:
Herzliya

we are looking for an experienced Senior Hardware Board Design Engineer to join our R&D team in Kfar Saba.
This is a hands-on technical leadership role covering the complete hardware development lifecycle-from system architecture and board design through prototype bring-up, validation, and transfer to production.
What will you do?
Lead electronic board development for power and motion control applications, from initial concept through design release
Define hardware architecture, create schematics, select components, and lead design reviews
Own and manage the BOM, including cost-performance optimization, second sourcing, component substitutions, availability, and lifecycle analysis
Work closely with PCB layout engineers to define stack-up, routing rules, power and signal constraints, EMC/EMI requirements, and DFM considerations
Prepare and support prototype PCB and PCBA manufacturing, including documentation, fabrication files, supplier coordination, and build readiness
Perform board bring-up, laboratory debugging, hardware validation, and functional testing
Define and execute hardware verification and validation plans
Support firmware engineers during hardware and software integration
Incorporate DFM and DFT requirements, test points, and panelization considerations into the design
Support prototype, sample, and pilot production with subcontractors
Support the integration of electronic boards into mechanical housings and complete systems, including connectors, harnesses, and thermal constraints
Prepare and maintain production-ready technical documentation, including schematics, BOMs, and design notes
Mentor junior engineers, lead design reviews, and establish best practices for reliable and manufacturable hardware design

We're looking for a Director of Product Design to lead our product design group: 12 people across Core, New Business Lines and Internal Products, including two team leaders and close work with a dedicated UXR. Youll report directly to the CPO.

What Youll Do
Make design visible where decisions are made: Build a mechanism, not a mood. A forum, a recurring report, a metric you introduce, a ritual that puts the groups contribution in front of the executive team on a schedule and in business language. Get design into the conversation before prioritization.
Raise the bar on the group: Move designers from executing tickets to defining problems and bringing options. Tell the difference between a designer who is weak and a good one who is stuck, and handle them differently. Set expectations explicitly, in writing, and hold to them.
Lead the leaders: Manage two team leaders with different styles, mentor and grow them.
Scale the infrastructure: Own the design system as infrastructure rather than documentation. Close the design to code gap (Figma to Storybook, component usage visibility, token migration) and keep asking which parts of execution an agent can carry.
Tie every major move to a number: Know which KPI a design decision is meant to move, how its measured, what the baseline was, and what you do when it doesnt move.
Decide how much process each problem earns: A small change in a familiar area and a large one in a new domain dont get the same treatment. Calibrate by risk and by what the team already knows, and be able to explain the call.

Were looking for an exceptional Director of Product Design to lead our Product Design team and help define the next generation of AI-powered clinical experiences.
This is a player-coach leadership role. Youll lead and mentor a team of experienced Product Designers, while staying close to the work yourself. Youll help solve some of our most complex product and UX challenges to create products that clinicians trust, adopt, and love to use. Youll shape our design direction and raise the bar for product quality across .
What youll do:
Define and drive Product Design vision, principles, and strategy.
Lead, coach, and develop a team of three senior Product Designers.
Develop a deep understanding of clinical workflows and translate complex real-world challenges into simple, intuitive product experiences.
Stay hands-on with high-impact and complex design challenges, from discovery through execution.
Build a strong research-driven design culture centered on deep customer and workflow understanding.
Shape AI-native experiences that fit naturally into clinicians daily workflows.
Partner closely with Product, Engineering, Clinical, and Executive leadership to influence product strategy and priorities.
Establish and evolve best practices for UX research, usability testing, design systems, and continuous product validation.
Raise the bar for craft, consistency, and product experience across the organization.