לוח משרות דרושים

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving team behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHSIC Hardware Description Language (VHDL)), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of the Data Center silicon. Our portfolio spans CPU, TPU, Networking and other key data center technologies, which power our company's most demanding Compute and AI/ML applications. You will be a key contributor in the growth team, developing advanced custom IP and solutions. We seek experienced applicants with expertise in one or more of the following areas: wireline communications, analog circuit design, DSP design and algorithms, signal integrity, transmission line theory, advanced analog and mixed-signal modeling, high-speed clocking, Clock and Data Recovery (CDR), equalization, high-speed IO industry standards. You will collaborate with a set of cross-functional organizations. You will serve many of our companys advanced data center products.The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our companyservices around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Architecture and design of high-speed analog/digital circuits (ADC, DAC, PLL, CDR, DSP), including optimizing for Power, Performance, and Area (PPA).
Model and simulate channel behavior (S-parameters), signal integrity, and jitter using tools like MATLAB.
Bring up new silicon, characterizing performance, and testing for electrical compliance in lab environments.
Work with packaging, board design, and firmware teams to ensure integration into System-on-Chips (SoCs).
Adhere to standards like Institute of Electrical and Electronics Engineers(IEEE) or Optical Internetworking Forum (OIF) for protocols and optimizing power consumption.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilities
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up - FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving team behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define and drive the implementation of physical design methodologies.
Take ownership of one or more physical design partitions or top level.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design related rule sets for the functional design engineers.

Physical Design team within us is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Your Impact
You'll be part of the team, which is at the heart of our software and ASIC design efforts.

You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

We are seeking a CAD Engineer to join the Physical Design team.

You'll be joining our Physical Design team within us, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

You'll be joining the Israeli team which is the core center of our SW and ASIC design. You'll be part of the group driving our groundbreaking next-generation network devices. Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs. Join a team of dedicated engineers with a proven track-record at delivering breakthrough products. Our R&D center is outstanding - hosting all silicon HW and SW development teams inside one site. We are transforming the industry and building a new AI/ML Networks, as well as providing a unified, programmable silicon architecture that is the foundation of all our future routing products. Our devices are crafted to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed (50+ Terabits per second) without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

We are a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine! You have a unique opportunity to join the core center of our SW development and work with us to design and deliver breakthrough technologies

What You'll Do:

You'll be joining our Physical Design team, which is at the center of the silicon development. Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.

We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.

We are hiring a Senior PCIe Firmware to the Chip Design PCIe Firmware team. You will be joining a team whose primary mission is to work on groundbreaking technology network adapters and build the core technology of the next generation our devices in a wide range of fields - low-level C layer between HW and FWs, automation challenges, and Python testing environment.

What youll be doing:

implement FW and verification features in a pre and post silicon environments in the PCIe technology.

Collaborate with other teams in the PCIe group, software, and architecture teams to define and craft legacy and new low-level firmware verification methods.

Improve the existing automated process.

In this role, you will conduct Place and Route experiments and sensitivity analyses to influence standard cell library architecture, metal stack definitions, and design rules. You will collaborate with Foundry, IP, and Architecture teams to identify Power, Performance, and Area (PPA) bottlenecks and drive System Technology Co-Optimization (STCO) initiatives.
Your work will involve performing high-fidelity physical implementation sweeps, analyzing the impact of scaling boosters, and developing automated methodologies to quantify PPA gains. By navigating the trade-offs between process complexity and design performance, you will ensure our companys hardware achieves efficiency and power density.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Execute high-fidelity Place and Route experiments to evaluate the PPA impact of advanced process features, library architectures, and design rule variations on datacenter-class IP.
Drive Design Technology Co-Optimization by collaborating with foundries and internal technology teams to define optimal metal stacks, track heights, and scaling boosters (e.g., backside power delivery, buried power rails).
Quantify process entitlement through systematic benchmarking of logic and memory macros, identifying bottlenecks in power density and timing closure for next-generation nodes.
Develop automated physical design methodologies and flows to accelerate technology pathfinding and enable rapid what-if analysis of emerging transistor architectures.
Influence System Technology Co-Optimization by partnering with Hardware Architects and Circuit Designers to translate process-level innovations into system-level performance gains.

we are looking for a technically sharp, customer-focused Solutions Architect to help drive adoption of our blazing-fast real-time data platform. In this high-impact role, youll partner closely with our sales team to win business by translating complex technical capabilities into clear, compelling value for our customers.
Based in Israel, youll serve as the technical expert and strategic advisor throughout the sales process - from discovery to demo to deployment. Whether its architecting a high-scale solution, answering in-depth questions, or running a proof of concept, your expertise will be key to helping customers realize the power .
This is a pre-sales position.
Responsibilities:
Preparing and developing technical presentations to explain our company's products or services to customers.
Discussing equipment needs and system requirements with customers and engineers.
Collaborating with sales teams to understand customer requirements and provide sales support.
Researching, developing, and identifying modifying products to meet customers' technical requirements and needs.
Soliciting and logging client feedback and evaluating the data to create new sales and marketing strategies to target customers.
Identifying areas for improvement and communicating these issues as well as possible solutions to upper management, including product managers.
Setting and achieving sales goals and quotas.
Training other members of the sales team on the technical aspects of the company's products and services.

We are seeking a highly experienced Technical Field Architect to join our CTO team, working onsite in our Tel Aviv and Haifa offices in Israel. This is a critical role, facilitating communication and product adoption by the Office of the CTO and other field teams by working closely with our R&D teams to bring product development advances to the field.
The ideal candidate will have a deep understanding of both GTM and R&D processes, and be able to dive into the technical details of new products as they are developed. This person will communicate regularly with colleagues in the Office of the CTO, as well as sales engineering leaders and product management, to ensure rollout of releases and features are well-understood by our field teams and their customers. This person will work with the field and customers to ensure features are developed with customer requirements in mind, and work with engineering and architects to understand the detailed implementation of features.
Responsibilities:
Regularly meet with R&D teams responsible for feature design and development, ensuring alignment with customer requirements and field teams
Understand and help document product development and release processes and timelines
Develop and lead technical presentations for field teams
Work closely with colleagues in both R&D and the Office of the CTO to streamline communication and establishing close alignment
Install pre-release SW and give engineering feedback.

we are looking for a Senior Software Architect Bayretail.
What Youll Do:
Drive the execution and delivery of product features by collaborating with cross-functional teams
Lead key engineering initiatives to improve overall engineering effectiveness and productivity
Iteratively define and refine development processes and engineering best practices as teams grow
Recruit, challenge, and reward high-performing software engineers and managers.
Work in an agile, small team environment with a focus on speed and quality
Be a trusted partner for senior management to determine the best solutions, help drive alignment and implement decisions throughout your team
Pre-sales Support; including solution workshops and POCs, written responses, and relationship building

Required Fraud Lead (Technical Architect)
Tel Aviv-Yafo, Gush Dan, Israel
We offer the industrys only platform that fuses customer identity and anti-fraud solutions - customer identity management, identity verification, and fraud prevention.
We sell to industries with large, consumer-facing businesses such as: banking, financial services, insurance, fintech, gaming, ecommerce/retail, telco / media, utilities, etc.
About the Role:
The Fraud Lead is the principal technical authority for our fraud detection and response engine. You own the professional logic that powers our product, ensuring that the "Brain" of our platform is technically cohesive, scientifically rigorous, and market-leading.
You act as a System Architect for the fraud domain, connecting the dots between Research, Data Science, and Analytics. Crucially, you serve as the primary technical consultant for our customers, helping them understand, integrate, and optimize the fraud logic that protects their environments. You work alongside a separate Product group (who defines the roadmap) and a Platform Engineering group (who builds the infrastructure).
What youll do:
Technical Domain Architecture
Logic Blueprinting: Design the end-to-end technical logic for detection features-from telemetry ingestion to real-time response actions.
Cross-Team "Glue": Ensure that Fraud Research insights are effectively operationalized by the Data Science team and surfaced correctly by the Analytics team.
Architecture Governance: Set the technical standards for how detection logic is built, ensuring it is scalable and compatible with the Platform Engineering teams infrastructure.
Customer Fronting & Technical Advisory
Technical Subject Matter Expert: Act as the lead technical consultant for high-value customers. You will lead "deep-dive" sessions with client-side engineers and fraud experts to explain our detection methodologies and data requirements.
Integration Strategy: Advise customers on how to best leverage our technical logic within their specific business contexts.
Feedback Loop: Translate complex customer technical needs and "edge case" fraud patterns back into technical requirements for the internal fraud group.
Expert Implementation
Hands-on Prototyping: Remain an expert practitioner in Python and SQL. You will prototype new detection methodologies and perform technical validation of production models.
Quality & Observability: Design the technical frameworks that ensure our detection logic remains performant and observable in live customer environments.